M55800A Atmel Corporation, M55800A Datasheet - Page 10
M55800A
Manufacturer Part Number
M55800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M55800A.pdf
(29 pages)
4.M55800A.pdf
(256 pages)
5.M55800A.pdf
(28 pages)
Specifications of M55800A
Flash (kbytes)
0 Kbytes
Pin Count
176
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
58
Ext Interrupts
58
Usb Speed
No
Usb Interface
No
Spi
1
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
72
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
List of Tables
x
Table 4-3
Table 4-4
Table 5-1
Table 6-1
Table 6-2
Table 6-3
Table 6-4
Table 6-5
Table 6-6
Table 6-7
Table 6-8
Table 6-9
Table 6-10
Table 6-11
Table 6-12
Table 6-13
Table 6-14
Table 6-15
Table 6-16
Table 6-17
Table 6-18
Table 6-19
Table 6-20
Table 6-21
Table 6-22
Table 6-23
Table 7-1
Table 7-2
Table 7-3
Table 7-4
Table 7-5
Table 7-6
Table 7-7
Table 7-8
Table 7-9
Table 7-10
Table 7-11
Table 7-12
Table 7-13
Table 7-14
Table 7-15
Table 7-16
Table 7-17
Table 7-18
Table 7-19
Table 7-20
Table 7-21
Summary of coprocessor signaling ........................................................................... 4-7
Mode identifier signal meanings (nTRANS) ............................................................ 4-17
DCC register access instructions ............................................................................ 5-17
Branch instruction cycle operations .......................................................................... 6-4
Thumb long branch with link ..................................................................................... 6-5
Branch and exchange instruction cycle operations .................................................. 6-6
Data operation instruction cycles .............................................................................. 6-8
Multiply instruction cycle operations ......................................................................... 6-9
Multiply accumulate instruction cycle operations ...................................................... 6-9
Multiply long instruction cycle operations ............................................................... 6-10
Multiply accumulate long instruction cycle operations ............................................ 6-10
Load register instruction cycle operations .............................................................. 6-13
MAS[1:0] signal encoding ....................................................................................... 6-13
Store register instruction cycle operations .............................................................. 6-14
Load multiple registers instruction cycle operations ............................................... 6-15
Store multiple registers instruction cycle operations ............................................... 6-17
Data swap instruction cycle operations .................................................................. 6-18
Software Interrupt instruction cycle operations ....................................................... 6-19
Coprocessor data operation instruction cycle operations ....................................... 6-20
Coprocessor data transfer instruction cycle operations .......................................... 6-21
coprocessor data transfer instruction cycle operations ........................................... 6-23
Coprocessor register transfer, load from coprocessor ............................................ 6-25
Coprocessor register transfer, store to coprocessor ............................................... 6-26
Undefined instruction cycle operations ................................................................... 6-27
Unexecuted instruction cycle operations ................................................................ 6-28
ARM instruction speed summary ............................................................................ 6-29
General timing parameters ....................................................................................... 7-5
ABE control timing parameters ................................................................................. 7-6
Bidirectional data write cycle timing parameters ....................................................... 7-7
Bidirectional data read cycle timing parameters ....................................................... 7-8
Data bus control timing parameters .......................................................................... 7-9
Output 3-state time timing parameters ................................................................... 7-10
Unidirectional data write cycle timing parameters .................................................. 7-11
Unidirectional data read cycle timing parameters ................................................... 7-12
Configuration pin timing parameters ....................................................................... 7-13
Coprocessor timing parameters .............................................................................. 7-14
Exception timing parameters .................................................................................. 7-15
Synchronous interrupt timing parameters ............................................................... 7-16
Debug timing parameters ....................................................................................... 7-17
DCC output timing parameters ............................................................................... 7-19
Breakpoint timing parameters ................................................................................. 7-20
TCK and ECLK timing parameters ......................................................................... 7-21
MCLK timing parameters ........................................................................................ 7-22
Boundary scan general timing parameters ............................................................. 7-23
Reset period timing parameters .............................................................................. 7-24
Output enable and disable timing parameters ........................................................ 7-25
ALE address control timing parameters .................................................................. 7-26
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ARM DDI 0029G