M55800A Atmel Corporation, M55800A Datasheet - Page 186
M55800A
Manufacturer Part Number
M55800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M55800A.pdf
(29 pages)
4.M55800A.pdf
(256 pages)
5.M55800A.pdf
(28 pages)
Specifications of M55800A
Flash (kbytes)
0 Kbytes
Pin Count
176
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
58
Ext Interrupts
58
Usb Speed
No
Usb Interface
No
Spi
1
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
72
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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AC and DC Parameters
7.11
7-14
Coprocessor timing
Figure 7-10 shows the ARM7TDMI processor coprocessor timing. The timing
parameters used in Figure 7-10 are listed in Table 7-10.
In Figure 7-10, usually nMREQ and SEQ become valid T
MCLK. In this cycle the core has been busy-waiting for a coprocessor to complete the
instruction. If CPA and CPB change during phase 1, the timing of nMREQ and SEQ
depends on T
2, and so the timing of nMREQ and SEQ is always T
nMREQ
MCLK
nCPI
SEQ
CPA
CPB
Note
Copyright © 1994-2001. All rights reserved.
cpms
. Most systems can generate CPA and CPB during the previous phase
Symbol
T
T
T
T
T
cph
cpi
cpih
cpms
cps
Phase 1
T
cpi
Parameter
CPA,CPB hold time from MCLKr
MCLKf to nCPI valid
nCPI hold time from MCLKf
CPA, CPB to nMREQ, SEQ
CPA, CPB setup to MCLKr
T
cpms
T
cps
Table 7-10 Coprocessor timing parameters
T
cph
Phase 2
Figure 7-10 Coprocessor timing
msd
.
T
msd
cpih
after the falling edge of
Parameter type
Minimum
Maximum
Minimum
Maximum
Minimum
ARM DDI 0029G
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