M55800A Atmel Corporation, M55800A Datasheet - Page 242
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M55800A
Manufacturer Part Number
M55800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M55800A.pdf
(29 pages)
4.M55800A.pdf
(256 pages)
5.M55800A.pdf
(28 pages)
Specifications of M55800A
Flash (kbytes)
0 Kbytes
Pin Count
176
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
58
Ext Interrupts
58
Usb Speed
No
Usb Interface
No
Spi
1
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
72
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Debug in Depth
B.8
B.8.1
B-24
Determining the core and system state
Determining the core state
When the ARM7TDMI core is in debug state, you examine the core and system state
by forcing the load and store multiples into the instruction pipeline.
Before you can examine the core and system state, the debugger must determine if the
processor entered debug from Thumb state or ARM state, by examining bit 4 of the
EmbeddedICE debug status register. When bit 4 is HIGH, the core has entered debug
from Thumb state, when bit 4 is LOW, the core has entered debug entered from ARM
state.
When the processor has entered debug state from Thumb state, the simplest course of
action is for the debugger to force the core back into ARM state. The debugger can then
execute the same sequence of instructions to determine the processor state.
To force the processor into ARM state while in debug, execute the following sequence
of Thumb instructions on the core:
Because all Thumb instructions are only 16 bits long, the simplest course of action,
when shifting scan chain 1, is to repeat the instruction. For example, the encoding for
to keep track of the half of the bus on which the processor expects to read the data.
You can use the sequences of ARM instructions in Example B-1 and Example B-2 on
page B-25 to determine the state of the processor.
With the processor in the ARM state, the instruction to execute is shown in
Example B-1.
is
Note
Copyright © 1994-2001. All rights reserved.
, so when
Example B-1 Instruction to determine core state
shifts into scan chain 1, the debugger does not have
ARM DDI 0029G
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