M55800A Atmel Corporation, M55800A Datasheet - Page 14
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M55800A
Manufacturer Part Number
M55800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M55800A.pdf
(29 pages)
4.M55800A.pdf
(256 pages)
5.M55800A.pdf
(28 pages)
Specifications of M55800A
Flash (kbytes)
0 Kbytes
Pin Count
176
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
58
Ext Interrupts
58
Usb Speed
No
Usb Interface
No
Spi
1
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
72
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
List of Figures
xiv
Figure 3-11
Figure 3-12
Figure 3-13
Figure 3-14
Figure 3-15
Figure 3-16
Figure 3-17
Figure 3-18
Figure 3-19
Figure 3-20
Figure 3-21
Figure 3-22
Figure 4-1
Figure 4-2
Figure 4-3
Figure 4-4
Figure 4-5
Figure 4-6
Figure 4-7
Figure 5-1
Figure 5-2
Figure 5-3
Figure 5-4
Figure 5-5
Figure 5-6
Figure 7-1
Figure 7-2
Figure 7-3
Figure 7-4
Figure 7-5
Figure 7-6
Figure 7-7
Figure 7-8
Figure 7-9
Figure 7-10
Figure 7-11
Figure 7-12
Figure 7-13
Figure 7-14
Figure 7-15
Figure 7-16
Figure 7-17
Figure 7-18
Figure 7-19
Figure 7-20
Figure 7-21
Figure 7-22
External bus arrangement ...................................................................................... 3-17
Bidirectional bus timing ........................................................................................... 3-18
Unidirectional bus timing ......................................................................................... 3-18
External connection of unidirectional buses ........................................................... 3-19
Data write bus cycle ................................................................................................ 3-20
Data bus control circuit ........................................................................................... 3-20
Test chip data bus circuit ........................................................................................ 3-23
Memory access ....................................................................................................... 3-25
Two cycle memory access ...................................................................................... 3-26
Data replication ....................................................................................................... 3-28
Typical system timing ............................................................................................. 3-30
Reset sequence ...................................................................................................... 3-33
Coprocessor busy-wait sequence ............................................................................. 4-8
Coprocessor register transfer sequence ................................................................... 4-9
Coprocessor data operation sequence ................................................................... 4-10
Coprocessor load sequence ................................................................................... 4-11
Coprocessor connections with bidirectional bus ..................................................... 4-12
Coprocessor connections with unidirectional bus ................................................... 4-13
Connecting multiple coprocessors .......................................................................... 4-14
Typical debug system ............................................................................................... 5-4
ARM7TDMI block diagram ........................................................................................ 5-5
Debug state entry ..................................................................................................... 5-7
Clock switching on entry to debug state ................................................................. 5-10
ARM7TDM, TAP controller, and EmbeddedICE Logic ........................................... 5-13
DCC control register format .................................................................................... 5-16
General timing .......................................................................................................... 7-4
ABE control timing .................................................................................................... 7-6
Bidirectional data write cycle timing .......................................................................... 7-7
Bidirectional data read cycle timing .......................................................................... 7-8
Data bus control timing ............................................................................................. 7-9
Output 3-state timing .............................................................................................. 7-10
Unidirectional data write cycle timing ...................................................................... 7-11
Unidirectional data read cycle timing ...................................................................... 7-12
Configuration pin timing .......................................................................................... 7-13
Coprocessor timing ................................................................................................. 7-14
Exception timing ..................................................................................................... 7-15
Synchronous interrupt timing .................................................................................. 7-16
Debug timing ........................................................................................................... 7-17
DCC output timing .................................................................................................. 7-19
Breakpoint timing .................................................................................................... 7-20
TCK and ECLK timing ............................................................................................. 7-21
MCLK timing ........................................................................................................... 7-22
Boundary scan general timing ................................................................................ 7-23
Reset period timing ................................................................................................. 7-24
Output enable and disable times due to HIGHZ TAP instruction ............................ 7-25
Output enable and disable times due to data scanning .......................................... 7-25
ALE control timing ................................................................................................... 7-26
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