M55800A Atmel Corporation, M55800A Datasheet - Page 198
M55800A
Manufacturer Part Number
M55800A
Description
Manufacturer
Atmel Corporation
Datasheets
1.M40800.pdf
(284 pages)
2.M40800.pdf
(153 pages)
3.M55800A.pdf
(29 pages)
4.M55800A.pdf
(256 pages)
5.M55800A.pdf
(28 pages)
Specifications of M55800A
Flash (kbytes)
0 Kbytes
Pin Count
176
Max. Operating Frequency
33 MHz
Cpu
ARM7TDMI
Hardware Qtouch Acquisition
No
Max I/o Pins
58
Ext Interrupts
58
Usb Speed
No
Usb Interface
No
Spi
1
Uart
3
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
72
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
8
Self Program Memory
NO
External Bus Interface
1
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.3/5.0
Fpu
No
Mpu / Mmu
no / no
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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AC and DC Parameters
7.22
7-26
Address latch enable control
Figure 7-22 shows the ARM7TDMI reset period timing. The timing parameters used in
Figure 7-22 are listed in Table 7-21.
In Figure 7-22, T
address in phase 2. If ALE is driven LOW after T
is known as address breakthrough.
Note
Copyright © 1994-2001. All rights reserved.
MAS[1:0]
nTRANS
ald
A[31:0]
MCLK
LOCK
nOPC
is the time by which ALE must be driven LOW to latch the current
nRW
ALE
Symbol
T
T
T
ald
ale
aleh
Table 7-21 ALE address control timing parameters
Parameter
Address group latch output time
Address group latch open output delay
Address group latch output hold time
Phase 1
T
ale
ald
, then a new address is latched. This
T
aleh
Figure 7-22 ALE control timing
T
ald
Phase 2
ARM DDI 0029G
Maximum
Maximum
Minimum
Parameter
type
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