SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 25
Manufacturer Part Number
Specifications of SAM4S16C
# Of Touch Channels
Hardware Qtouch Acquisition
Max I/o Pins
Quadrature Decoder Channels
Sd / Emmc
Adc Resolution (bits)
Adc Speed (ksps)
Resistive Touch Screen
Dac Resolution (bits)
Self Program Memory
External Bus Interface
Temp. Range (deg C)
-40 to 85
I/o Supply Class
Operating Voltage (vcc)
1.62 to 3.6
Mpu / Mmu
Yes / No
Output Compare Channels
Input Capture Channels
Calibrated Rc Oscillator
1. If PB12 is used as PIO input in user applications, a low level must be ensured at startup to prevent Flash erase before the
2. In the product Datasheet Refer to: “Slow Clock Generator” of the “Supply Controller” section.
3. In the product Datasheet Refer to: “3 to 20 MHZ Crystal Oscillator” information in the “PMC” section.
Serial Wire JTAG Debug Port (SWJ-DP) Pins
user application sets PB12 into PIO mode,
System I/O Configuration Pin List.
The SWJ-DP pins are TCK/SWCLK, TMS/SWDIO, TDO/SWO, TDI and commonly provided on
a standard 20-pin JTAG connector defined by ARM. For more details about voltage reference
and reset state, refer to
At startup, SWJ-DP pins are configured in SWJ-DP mode to allow connection with debugging
probe. Please refer to the “Debug and Test” Section of the product datasheet.
SWJ-DP pins can be used as standard I/Os to provide users more general input/output pins
when the debug port is not needed in the end application. Mode selection between SWJ-DP
mode (System IO mode) and general IO mode is performed through the AHB Matrix Special
Function Registers (MATRIX_SFR). Configuration of the pad for pull-up, triggers, debouncing
and glitch filters is possible regardless of the mode.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It
integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left uncon-
nected for normal operations.
By default, the JTAG Debug Port is active. If the debugger host wants to switch to the Serial
Wire Debug Port, it must provide a dedicated JTAG sequence on TMS/SWDIO and
TCK/SWCLK which disables the JTAG-DP and enables the SW-DP. When the Serial Wire
Debug Port is active, TDO/TRACESWO can be used for trace.
The asynchronous TRACE output (TRACESWO) is multiplexed with TDO. So the asynchronous
trace can only be used with SW-DP, not JTAG-DP. For more information about SW-DP and
JTAG-DP switching, please refer to the “Debug and Test” Section.
Table 3-1 on page
Low Level at startup
Configuration Register in the “Bus
In Matrix User Interface Registers
Matrix” section of the datasheet.)
(Refer to the System I/O