SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 542
Manufacturer Part Number
Specifications of SAM4S16C
# Of Touch Channels
Hardware Qtouch Acquisition
Max I/o Pins
Quadrature Decoder Channels
Sd / Emmc
Adc Resolution (bits)
Adc Speed (ksps)
Resistive Touch Screen
Dac Resolution (bits)
Self Program Memory
External Bus Interface
Temp. Range (deg C)
-40 to 85
I/o Supply Class
Operating Voltage (vcc)
1.62 to 3.6
Mpu / Mmu
Yes / No
Output Compare Channels
Input Capture Channels
Calibrated Rc Oscillator
Figure 28-4. Output Line Timings
Write PIO_ODSR at 1
Write PIO_ODSR at 0
Output Line Timings
Input Glitch and Debouncing Filters
After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0.
directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is
The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This reg-
ister indicates the level of the I/O lines regardless of their configuration, whether uniquely as an
input or driven by the PIO controller or driven by a peripheral.
Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise
PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
Optional input glitch and debouncing filters are independently programmable on each I/O line.
The glitch filter can filter a glitch with a duration of less than 1/2 Master Clock (MCK) and the
debouncing filter can filter a pulse of less than 1/2 Period of a Programmable Divided Slow
The selection between glitch filtering or debounce filtering is done by writing in the registers
PIO_IFSCDR (PIO Input Filter Slow Clock Disable Register) and PIO_IFSCER (PIO Input Filter
Slow Clock Enable Register). Writing PIO_IFSCDR and PIO_IFSCER respectively, sets and
clears bits in PIO_IFSCSR.
The current selection status can be checked by reading the register PIO_IFSCSR (Input Filter
Slow Clock Status Register).
For the debouncing filter, the Period of the Divided Slow Clock is performed by writing in the DIV
field of the PIO_SCDR (Slow Clock Divider Register)
• If PIO_IFSCSR[i] = 0: The glitch filter can filter a glitch with a duration of less than 1/2 Period
• If PIO_IFSCSR[i] = 1: The debouncing filter can filter a pulse with a duration of less than 1/2
of Master Clock.
Period of the Programmable Divided Slow Clock.
shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by
also shows when the feedback in PIO_PDSR is available.