SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 920
Manufacturer Part Number
Specifications of SAM4S16C
# Of Touch Channels
Hardware Qtouch Acquisition
Max I/o Pins
Quadrature Decoder Channels
Sd / Emmc
Adc Resolution (bits)
Adc Speed (ksps)
Resistive Touch Screen
Dac Resolution (bits)
Self Program Memory
External Bus Interface
Temp. Range (deg C)
-40 to 85
I/o Supply Class
Operating Voltage (vcc)
1.62 to 3.6
Mpu / Mmu
Yes / No
Output Compare Channels
Input Capture Channels
Calibrated Rc Oscillator
Source Clock Selection Criteria
Changing the Duty-Cycle, the Period and the Dead-Times
The large number of source clocks can make selection difficult. The relationship between the
value in the
Period Register gives the PWM accuracy. The Duty-Cycle quantum cannot be lower than
1/CPRDx value. The higher the value of PWM_CPRDx, the greater the PWM accuracy.
For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value
from between 1 up to 14 in PWM_CDTYx Register. The resulting duty-cycle quantum cannot be
lower than 1/15 of the PWM period.
It is possible to modulate the output waveform duty-cycle, period and dead-times.
To prevent unexpected output waveform, the user must use the
Time Update Register”
waveform parameters while the channel is still enabled.
• If the channel is an asynchronous channel (SYNCx = 0 in
• If the channel is a synchronous channel and update method 0 is selected (SYNCx = 1 and
• If the channel is a synchronous channel and update method 1 or 2 is selected (SYNCx=1 and
values until the end of the current PWM period and update the values for the next period.
UPDM = 0 in PWM_SCM register), these registers hold the new period, duty-cycle and dead-
times values until the bit UPDULOCK is written at “1” (in
values for the next period.
UPDM=1 or 2 in PWM_SCM register):
– registers PWM_CPRDUPDx and PWM_DTUPDx hold the new period and dead-
– register PWM_CDTYUPDx holds the new duty-cycle value until the end of the
times values until the bit UPDULOCK is written at “1” (in PWM_SCUC register) and
the end of the current PWM period, then update the values for the next period.
update period of synchronous channels (when UPRCNT is equal to UPR in
Sync Channels Update Period Register”
PWM period, then updates the value for the next period.
If the update registers PWM_CDTYUPDx, PWM_CPRDUPDx and PWM_DTUPDx are written
several times between two updates, only the last written value is taken into account.
“PWM Channel Period Register”
(PWM_SCM)), these registers hold the new period, duty-cycle and dead-times
(PWM_CDTYx) can help the user in choosing. The event number written in the
(PWM_SCUC)) and the end of the current PWM period, then update the
“PWM Channel Period Update Register”
(PWM_CDTYUPDx, PWM_CPRDUPDx and PWM_DTUPDx) to change
(PWM_CPRDx) and the
(PWM_SCUP)) and the end of the current
“PWM Sync Channels Update
“PWM Sync Channels Mode
“PWM Channel Duty Cycle
“PWM Channel Dead
“PWM Channel Duty