SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 673

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

38.11.11 LCD Timing Configuration Register 1
Name:
Address:
Access:
Reset:
• VFP: Vertical Front Porch
In TFT mode, these bits equal the number of idle lines at the end of the frame.
In STN mode, these bits should be set to 0.
• VBP: Vertical Back Porch
In TFT mode, these bits equal the number of idle lines at the beginning of the frame.
In STN mode, these bits should be set to 0.
• VPW: Vertical Synchronization pulse width
In TFT mode, these bits equal the vertical synchronization pulse width, given in number of lines. LCDVSYNC width is equal
to (VPW+1) lines.
In STN mode, these bits should be set to 0.
• VHDLY: Vertical to horizontal delay
In TFT mode, this is the delay between LCDVSYNC rising or falling edge and LCDHSYNC rising edge. Delay is
(VHDLY+1) LCDDOTCK cycles. Bit 31 must be written to 1.
In STN mode, these bits should be set to 0.
6462B–ATARM–6-Sep-11
6462B–ATARM–6-Sep-11
31
23
15
1
–
7
LCDTIM1
0x00600808
Read-write
0x0000000
30
22
14
–
–
6
29
21
13
–
5
28
20
12
–
4
VBP
VFP
27
19
11
3
VPW
26
18
10
2
VHDLY
25
17
9
1
SAM9G10
SAM9G10
24
16
8
0
675
675