SAM9G10 Atmel Corporation, SAM9G10 Datasheet
SAM9G10
Specifications of SAM9G10
Related parts for SAM9G10
SAM9G10 Summary of contents
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Features • Core ® – ARM926EJ-S™ ARM Thumb – 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit • Memories – One 64-Kbyte internal ROM embedding bootstrap routine: Boot on NAND Flash, ® SDCard, DataFlash or serial DataFlash. ...
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Description The SAM9G35 is a member of the Atmel series of 400 MHz ARM926 embedded MPUs that sup- port high bandwidth communication and advanced user interfaces and are optimized for industrial applications such as building automation, data loggers, POS ...
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Block Diagram Figure 2-1. SAM9G35 Block Diagram 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 PIO PIO SAM9G35 SAM9G35 3 3 ...
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Signal Description Table 3-1 Table 3-1. Signal Description List Signal Name Function XIN Main Oscillator Input XOUT Main Oscillator Output XIN32 Slow Clock Oscillator Input XOUT32 Slow Clock Oscillator Output VBG Bias Voltage Reference for USB PCK0-PCK1 Programmable Clock ...
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Table 3-1. Signal Description List (Continued) Signal Name Function D0-D15 Data Bus D16-D31 Data Bus A0-A25 Address Bus NWAIT External Wait Signal NCS0-NCS5 Chip Select Lines NWR0-NWR3 Write Signal NRD Read Signal NWE Write Enable NBS0-NBS3 Byte Mask Signal NFD0-NFD16 ...
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Table 3-1. Signal Description List (Continued) Signal Name Function Universal Synchronous Asynchronous Receiver Transmitter - USARTx SCKx USARTx Serial Clock TXDx USARTx Transmit Data RXDx USARTx Receive Data RTSx USARTx Request To Send CTSx USARTx Clear To Send UTXDx UARTx ...
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Table 3-1. Signal Description List (Continued) Signal Name Function PWM0-PWM3 Pulse Width Modulation Output HFSDPA USB Host Port A Full Speed Data + HFSDMA USB Host Port A Full Speed Data - HHSDPA USB Host Port A High Speed Data ...
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Table 3-1. Signal Description List (Continued) Signal Name Function AD0 Top/Upper Left Channel XP_UL AD1 Bottom/Upper Right Channel XM_UR AD2 Right/Lower Left Channel YP_LL AD3 Left/Sense Channel YM_SENSE AD4 Lower Right Channel LR AD5-AD11 7 Analog Inputs ADTRG ADC Trigger ...
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I/O Description Table 4-1. I/O Type GPIO GPIO_CLK GPIO_CLK2 GPIO_ANA EBI EBI_O EBI_CLK RSTJTAG SYSC VBG USBFS USBHS CLOCK DIB When “Reset State” is mentioned, the configuration is defined by the “Reset State” column of the Pin Description table. ...
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Table 4-2. I/O Type USBFS USBHS CLOCK DIB 4.2.1 Reset State In the tables that follow, the column “Reset State” indicates the reset state of the line with mnemonics. • “PIO” “/” signal Indicates whether the PIO Line resets in ...
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BGA Package Pinout Table 4-3. Pin Description BGA217 Ball Power Rail I/O Type Signal VDDIOP0 GPIO PA0 L3 VDDIOP0 GPIO PA1 P1 VDDIOP0 GPIO PA2 L4 VDDIOP0 GPIO PA3 N4 VDDIOP0 GPIO PA4 T3 VDDIOP0 GPIO PA5 R1 ...
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Table 4-3. Pin Description BGA217 (Continued) Primary Ball Power Rail I/O Type Signal VDDIOP0 GPIO PA21 T6 VDDIOP0 GPIO PA22 R6 VDDIOP0 GPIO_CLK PA23 U7 VDDIOP0 GPIO PA24 T7 VDDIOP0 GPIO PA25 T8 VDDIOP0 GPIO PA26 R7 VDDIOP0 GPIO PA27 ...
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Table 4-3. Pin Description BGA217 (Continued) Ball Power Rail I/O Type Signal VDDANA GPIO_ANA PB12 B4 VDDANA GPIO_ANA PB13 A2 VDDANA GPIO_ANA PB14 C4 VDDANA GPIO_ANA PB15 C3 VDDANA GPIO_ANA PB16 A1 VDDANA GPIO_ANA PB17 B1 VDDANA GPIO PB18 D5 ...
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Table 4-3. Pin Description BGA217 (Continued) Primary Ball Power Rail I/O Type Signal VDDIOP1 GPIO PC16 J1 VDDIOP1 GPIO PC17 L1 VDDIOP1 GPIO PC18 K2 VDDIOP1 GPIO PC19 N3 VDDIOP1 GPIO PC20 K1 VDDIOP1 GPIO PC21 M3 VDDIOP1 GPIO PC22 ...
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Table 4-3. Pin Description BGA217 (Continued) Ball Power Rail I/O Type Signal N17 VDDNF EBI PD10 N15 VDDNF EBI PD11 K15 VDDNF EBI PD12 M15 VDDNF EBI PD13 L14 VDDNF EBI PD14 M16 VDDNF EBI PD15 L16 VDDNF EBI PD16 ...
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Table 4-3. Pin Description BGA217 (Continued) Primary Ball Power Rail I/O Type Signal T16 GNDUTMI GND GNDUTMI D14 VDDIOM EBI D0 D15 VDDIOM EBI D1 A16 VDDIOM EBI D2 B16 VDDIOM EBI D3 A17 VDDIOM EBI D4 B15 VDDIOM EBI ...
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Table 4-3. Pin Description BGA217 (Continued) Ball Power Rail I/O Type Signal E14 VDDIOM EBI_O A19 B9 VDDIOM EBI_O NCS0 B8 VDDIOM EBI_O NCS1 D9 VDDIOM EBI_O NRD C9 VDDIOM EBI_O NWR0 C7 VDDIOM EBI_O NWR1 VDDIOM EBI_O NWR3 A8 ...
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Table 4-3. Pin Description BGA217 (Continued) Primary Ball Power Rail I/O Type Signal B7 VDDBU SYSC TST U10 VDDIOP0 RSTJTAG TCK T9 VDDIOP0 RSTJTAG TDI T10 VDDIOP0 RSTJTAG TDO U11 VDDIOP0 RSTJTAG TMS R10 VDDIOP0 RSTJTAG RTCK P10 VDDIOP0 RSTJTAG ...
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Memories Figure 6-1. SAM9G35 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1 DDR2/LPDDR SDR/LPSDR 0x2FFF FFFF 0x3000 0000 EBI Chip Select 2 ...
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Memory Mapping A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 ...
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Multiple device adaptability – Control signals programmable setup, pulse and hold time for each Memory Bank • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time • Slow Clock mode ...
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System Controller The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure ...
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Figure 7-1. SAM9G35 System Controller Block Diagram periph_irq[2..30] pit_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset SHDN WKUP XIN32 SLOW CLOCK XOUT32 OSC XIN 12MHz MAIN OSC XOUT UPLL PLLA periph_nreset periph_nreset periph_clk[2..3] ...
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Chip Identification • Chip ID: 0x819A_05A1 • Chip ID Extension: 1 • JTAG ID: 0x05B2_F03F • ARM926 TAP ID: 0x0792_603F 7.2 Backup Section The SAM9G35 features a Backup Section that embeds: • RC Oscillator • Slow Clock Oscillator • ...
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Peripherals 8.1 Peripheral Mapping As shown in space between the addresses 0xF000 0000 and 0xFFFF C000. Each User Peripheral is allocated 16 Kbytes of address space. 8.2 Peripheral Identifiers Table 8-1 for the control of the peripheral interrupt with ...
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Table 8-1. Instance 8.3 Peripheral Signal Multiplexing on I/O Lines The SAM9G35 features 4 PIO Controllers, PIOA, PIOB, PIOC and PIOD, which multiplex the I/O lines of the peripheral set. Each PIO Controller ...
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SAM9G35 SAM9G35 27 27 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ...
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SAM9G35 SAM9G35 28 28 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ...
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ARM926EJ-S 9.1 Description The ARM926EJ-S processor is a member of the ARM9 sors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multi- tasking applications where full memory management, high performance, low die size and low ...
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Write-though and Write-back Operation for DCache Only – Pseudo-random or Round-robin Replacement – Cache Lockdown Registers – Cache Maintenance • Write Buffer – 16-word Data Buffer – 4-address Address Buffer – Software Control Drain • DCache Write-back Buffer – ...
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Block Diagram Figure 9-1. ARM926EJ-S Internal Functional Block Diagram CP15 System Configuration Coprocessor Write Data DTCM Interface Data TCM Data Cache 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 External Coprocessors External Coprocessor Interface ARM9EJ-S Processor Core Read Data Data Instruction Address MMU Instruction Data ...
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ARM9EJ-S Processor 9.4.1 ARM9EJ-S Operating States The ARM9EJ-S processor can operate in three different states, each with a specific instruction set: • ARM state: 32-bit, word-aligned ARM instructions. • THUMB state: 16-bit, halfword-aligned Thumb instructions. • Jazelle state: variable ...
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Minimum interrupt latency is maintained across both ARM state and Java state. Since byte codes execution can be restarted, an interrupt automatically triggers the core to switch from Java state to ARM state for the execution of the interrupt handler. ...
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Table 9-1. ARM9TDMI Modes and Registers Layout (Continued) User and System Mode Supervisor Mode R12 R12 R13 R13_SVC R14 R14_SVC PC PC CPSR CPSR SPSR_SVC The ARM state register set contains 16 directly-accessible registers r15, and an additional ...
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There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see the ARM9EJ-S Technical Reference Manual, revision r1p2 page 2-12). 9.4.7.1 Status Registers The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers ...
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More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen excep- tions according to the following priority order: • Reset (highest priority) • Data Abort • FIQ • IRQ • Prefetch Abort • BKPT, Undefined ...
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The breakpoint (BKPT) instruction is a new feature of ARM9EJ-S that is destined to solve the problem of the Prefetch Abort. A breakpoint instruction operates as though the instruction caused a Prefetch Abort. A breakpoint instruction does not cause the ...
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Table 9-2. Mnemonic LDRBT LDRT LDM SWP MCR LDC CDP 9.4.9 New ARM Instruction Set Table 9-3. Mnemonic BXJ BLX SMLAxy SMLAL SMLAWy SMULxy SMULWy QADD QDADD QSUB QDSUB Notes: 9.4.10 Thumb Instruction Set Overview The Thumb instruction set is ...
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Load and Store multiple instructions • Exception-generating instruction For further details, see the ARM Technical Reference Manual. Table 9-4 Table 9-4. Mnemonic MOV ADD SUB CMP TST AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA ...
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Table 9-5. Register Notes: SAM9G35 SAM9G35 40 40 CP15 Registers Name ( Code (1) 0 Cache type (1) 0 TCM status 1 Control 2 Translation Table Base 3 Domain Access Control 4 Reserved (1) 5 Data fault Status ...
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CP15 Registers Access CP15 registers can only be accessed in privileged mode by: • MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15. • MRC (Move to ARM Register from Coprocessor) ...
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Memory Management Unit (MMU) The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide vir- tual memory features required by operating systems like Symbian OS, WindowsCE, and Linux. These virtual memory features are memory access permission controls ...
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Virtual Address), the access control logic determines if the access is permitted and outputs the appropriate physical address corresponding to the MVA. If access is not permitted, the MMU signals the CPU core to abort. If the TLB does ...
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The caches and the write buffer are controlled by the CP15 register 1 (Control), CP15 register 7 (cache operations) ...
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Write Buffer The ARM926EJ-S contains a write buffer that has a 16-word data buffer and a four- address buf- fer. The write buffer is used for all writes to a bufferable region, write-through region and write- back region. It ...
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Table 8 gives an overview of the supported transfers and different kinds of transactions they are used for. Table 9-7. Supported Transfers HBurst[2:0] Description SINGLE Single transfer INCR4 Four-word incrementing burst INCR8 Eight-word incrementing burst WRAP8 Eight-word wrapping burst 9.8.2 ...
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Debug and Test 10.1 Description The SAM9G35 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as down- loading code and single-stepping through programs. The Debug ...
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Block Diagram Figure 10-1. Debug and Test Block Diagram TAP: Test Access Port SAM9G35 SAM9G35 48 48 ICE/JTAG Boundary TAP Port ARM9EJ-S ICE-RT ARM926EJ-S DMA DBGU TMS TCK TDI NTRST JTAGSEL TDO RTCK POR Reset and TST Test DTXD ...
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Application Examples 10.4.1 Debug Environment Figure 10-2 standard debugging functions, such as downloading code and single-stepping through the pro- gram. A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing ...
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Test Environment Figure 10-3 ter. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 10-3. Application Test Environment Example SAM9G35 SAM9G35 ...
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Debug and Test Pin Description Table 10-1. Pin Name NRST TST NTRST TCK TDI TDO TMS RTCK JTAGSEL DRXD DTXD 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 Debug and Test Pin List Function Reset/Test Microcontroller Reset Test Mode Select ICE and JTAG Test Reset ...
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Functional Description 10.6.1 Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with ...
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Debug Unit The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with ...
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JTAG ID Code Register Access: Read-only 31 30 VERSION PART NUMBER 7 6 • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B2F • MANUFACTURER IDENTITY[11:1] ...
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Boot Strategies The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed thanks to the BMS pin. This allows the user to layout the ROM or an external memory to 0x0. ...
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Flow Diagram The ROM Code implements the algorithm shown below in Figure 11-1. ROM Code Algorithm Flow Diagram 11.3 Chip Setup At boot start-up, the processor clock (PCK) and the master clock (MCK) source is the 12 MHz Fast ...
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NVM Boot 11.4.1 NVM Boot Sequence The boot sequence on external memory devices can be controlled using the Boot Sequence Register (BSCR). The 3 LSBs of the BSCR are available to control the sequence. The user can then choose ...
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Figure 11-2. NVM Bootloader Sequence Diagram Device Setup SPI0 CS0 Flash Boot No SD Card Boot No NAND Flash Boot No SPI0 CS1 Flash Boot No TWI EEPROM Boot No SAM-BA Monitor SAM9G35 SAM9G35 Copy from ...
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NVM Bootloader Program Description Figure 11-3. NVM Bootloader Program Diagram The NVM bootloader program first initializes the PIOs related to the NVM device. Then it config- ures the right peripheral depending on the NVM and tries to access this ...
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If valid code is found, this code is loaded from NVM into internal SRAM and executed by branch- ing at address 0x0000_0000 after remap. This code may be the application code or a second- level bootloader. All the calls to ...
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The sixth vector, at offset 0x14, contains the size of the image to download. The user must replace this vector with the user’s own vector. This information is described below. Figure 11-7. Structure of the ARM Vector 6 31 The ...
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Figure 11-8. Boot NAND Flash Download SAM9G35 SAM9G35 62 62 Start Initialize NAND Flash interface Send Reset command No First page contains valid header Yes Read NAND Flash and PMECC parameters Read NAND Flash and PMECC parameters from the header ...
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NAND Flash Specific Header Detection This is the first method used to determine NAND Flash parameters. After Initialization and Reset command, the Boot Program reads the first page without ECC check, to determine if the NAND parameter header is present. ...
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ONFI 2.2 Parameters In case no valid header has been found, the Boot Program will check if the NAND Flash is ONFI compliant, sending a Read Id command (0x90) with 0x20 as parameter for the address. If the NAND Flash ...
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The PMECC descriptor structure is: typedef struct _PMECC_paramDesc_struct { } PMECC_paramDesc_struct; 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 unsigned int pageSize; unsigned int spareSize; unsigned int sectorSize for 512, 1 for 1024 ...
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The Galois field tables are mapped in the ROM just after the ROM code, as described in 11-9 below: Figure 11-9. Galois Field Table Mapping For a full description and an example of how to use the PMECC detection and ...
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Supported DataFlash Devices The SPI Flash Boot program supports all Atmel DataFlash devices. Table 11-2. Device AT45DB011 AT45DB021 AT45DB041 AT45DB081 AT45DB161 AT45DB321 AT45DB642 Supported Serial Flash Devices The SPI Flash Boot program supports all SPI Serial Flash devices responding correctly ...
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Before performing the jump to the application in internal SRAM, all the PIOs and peripherals used in the boot program are set to their reset state. Table 11-3. NVM Bootloader NAND SD Card SPI Flash TWI0 EEPROM SAM-BA Monitor 11.5 ...
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Figure 11-10. SAM-BA Monitor Diagram 11.5.1 Command List Table 11-4. Command • Mode commands: – Normal mode configures SAM-BA Monitor to send / receive data in binary format, ...
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Address: Address in hexadecimal. – Output: The byte, halfword or word read in hexadecimal followed by ‘>’ • Send a file (S): Send a file to a specified address. – Address: Address in hexadecimal. – Output: ‘>’ Note: • ...
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Figure 11-11. Xmodem Transfer Example 11.5.3 USB Device Port 11.5.3.1 Supported External Crystal / External Clocks The only frequency supported by SAM-BA Monitor to allow USB communication MHz crystal or external clock. 11.5.3.2 USB Class The device ...
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Table 11-5. Request GET_STATUS SET_FEATURE CLEAR_FEATURE The device also handles some class requests defined in the CDC class. Table 11-6. Request SET_LINE_CODING GET_LINE_CODING SET_CONTROL_LINE_STATE Unhandled requests are STALLed. 11.5.3.4 Communication Endpoints There are two communication endpoints and endpoint 0 is ...
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Boot Sequence Controller (BSC) 12.1 Description The System Controller embeds a Boot Sequence Configuration Register to save timeout delays on boot. The boot sequence is programmable through the Boot Sequence Configuration Regis- ter (BSCR). This register is powered by ...
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Boot Sequence Configuration Register Name: BSC_CR Address: 0xFFFFFE54 Access: Read-write Factory Value:0x0000_0000 • BOOTx: Boot media sequence Is defined in the product-dependent ROM code. • BOOTKEY 0xB5 (VALID): valid boot key ...
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Advanced Interrupt Controller (AIC) 13.1 Description The Advanced Interrupt Controller (AIC 8-level priority, individually maskable, vectored interrupt controller, providing handling thirty-two interrupt sources designed to sub- stantially reduce the software and real-time ...
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General Interrupt Mask – Provides Processor Synchronization on Events Without Triggering an Interrupt • Write Protected Registers 13.3 Block Diagram Figure 13-1. Block Diagram 13.4 Application Block Diagram Figure 13-2. Description of the Application Block SAM9G35 SAM9G35 76 76 ...
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AIC Detailed Block Diagram Figure 13-3. AIC Detailed Block Diagram 13.6 I/O Line Description Table 13-1. Pin Name FIQ IRQ0 - IRQn 13.7 Product Dependencies 13.7.1 I/O Lines The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed ...
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Interrupt Sources The Interrupt Source 0 is always located at FIQ. If the product does not feature ...
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The clear operation is perfunctory, as the software must perform an action to reinitialize the “memorization” circuitry activated when the source is programmed in edge-triggered mode. However, the set operation is available for auto-test or software debug purposes. It can ...
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Figure 13-5. External Interrupt Source Input Stage High/Low Source i Detector Set AIC_ISCR AIC_ICCR 13.8.2 Interrupt Latencies Global interrupt latencies depend on several parameters, including: • The time the software masks the interrupts. SAM9G35 SAM9G35 80 80 AIC_SMRi SRCTYPE Level/ ...
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Occurrence, either at the processor level or at the AIC level. • The execution time of the instruction in progress when the interrupt occurs. • The treatment of higher priority interrupts and the resynchronization of the hardware signals. This ...
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Figure 13-8. Figure 13-9. 13.8.3 Normal Interrupt 13.8.3.1 Priority Controller An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on the interrupt sources (except for those programmed in Fast ...
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AIC the end of the current service by writing the AIC_EOICR (End of Interrupt Command Register). The write of AIC_EOICR is the exit point of the interrupt handling. 13.8.3.2 Interrupt ...
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The Advanced Interrupt Controller has been programmed, AIC_SVR registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled. 2. The instruction at the ARM interrupt exception vector address is required to work with the vectoring LDR ...
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Fast Interrupt 13.8.4.1 Fast Interrupt Source The interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. The interrupt source 0 is generally connected to a ...
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In this case only, it de-asserts the nFIQ line on the processor. 4. The previous step enables branching to the corresponding interrupt service routine ...
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All enabled and pending interrupt sources that have the fast forcing feature enabled and that are programmed in edge-triggered mode must be cleared by writing to the Interrupt Clear Command Register. In doing so, they are cleared independently and thus ...
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To summarize, in normal operating mode, the read of AIC_IVR performs the following opera- tions within the AIC: 1. Calculates active interrupt (higher than current or spurious). 2. Determines and returns the vector of the active interrupt. 3. Memorizes the ...
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Write Protection Registers To prevent any single software error that may corrupt AIC behavior, the registers listed below can be write-protected by setting the WPEN bit in the (AIC_WPMR write access in a write-protected register is detected, ...
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Advanced Interrupt Controller (AIC) User Interface 13.10.1 Base Address The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This permits the vectoring fea- ture, as the PC-relative load/store instructions of the ARM ...
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AIC Source Mode Register Name: AIC_SMR0..AIC_SMR31 Address: 0xFFFFF000 Access Read-write Reset: 0x0 31 30 – – – – – – – SRCTYPE This register can only be written if the WPEN bit is ...
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AIC Source Vector Register Name: AIC_SVR0..AIC_SVR31 Address: 0xFFFFF080 Access: Read-write Reset: 0x0 This register can only be written if the WPEN bit is cleared in • VECTOR: Source Vector The user ...
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AIC Interrupt Vector Register Name: AIC_IVR Address: 0xFFFFF100 Access: Read-only Reset: 0x0 • IRQV: Interrupt Vector Register The Interrupt Vector Register contains the vector programmed by the user in the Source ...
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AIC FIQ Vector Register Name: AIC_FVR Address: 0xFFFFF104 Access: Read-only Reset: 0x0 • FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source ...
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AIC Interrupt Status Register Name: AIC_ISR Address: 0xFFFFF108 Access: Read-only Reset: 0x0 31 30 – – – – – – – – • IRQID: Current Interrupt Identifier The Interrupt Status Register returns the ...
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AIC Interrupt Pending Register Name: AIC_IPR Address: 0xFFFFF10C Access: Read-only Reset: 0x0 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Pending 0 = Corresponding interrupt is ...
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AIC Core Interrupt Status Register Name: AIC_CISR Address: 0xFFFFF114 Access: Read-only Reset: 0x0 31 30 – – – – – – – – • NFIQ: NFIQ Status 0 = nFIQ line is deactivated. ...
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AIC Interrupt Enable Command Register Name: AIC_IECR Address: 0xFFFFF120 Access: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Enable effect ...
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AIC Interrupt Disable Command Register Name: AIC_IDCR Address: 0xFFFFF124 Access: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Disable effect ...
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AIC Interrupt Clear Command Register Name: AIC_ICCR Address: 0xFFFFF128 Access: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Clear effect ...
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AIC Interrupt Set Command Register Name: AIC_ISCR Address: 0xFFFFF12C Access: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • FIQ, SYS, PID2-PID31: Interrupt Set effect ...
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AIC End of Interrupt Command Register Name: AIC_EOICR Address: 0xFFFFF130 Access: Write-only 31 30 – – – – – – – – The End of Interrupt Command Register is used by the interrupt ...
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AIC Spurious Interrupt Vector Register Name: AIC_SPU Address: 0xFFFFF134 Access: Read-write Reset: 0x0 This register can only be written if the WPEN bit is cleared in • SIVR: Spurious Interrupt Vector ...
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AIC Debug Control Register Name: AIC_DCR Address: 0xFFFFF138 Access: Read-write Reset: 0x0 31 30 – – – – – – – – This register can only be written if the WPEN bit is ...
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AIC Fast Forcing Enable Register Name: AIC_FFER Address: 0xFFFFF140 Access: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • SYS, PID2-PID31: Fast Forcing Enable effect ...
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AIC Fast Forcing Disable Register Name: AIC_FFDR Address: 0xFFFFF144 Access: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • SYS, PID2-PID31: Fast Forcing Disable effect ...
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AIC Fast Forcing Status Register Name: AIC_FFSR Address: 0xFFFFF148 Access: Read-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • SYS, PID2-PID31: Fast Forcing Status 0 = The Fast Forcing feature ...
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AIC Write Protect Mode Register Name: AIC_WPMR Address: 0xFFFFF1E4 Access: Read-write Reset: See Table 13 — — • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds ...
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AIC Write Protect Status Register Name: AIC_WPSR Address: 0xFFFFF1E8 Access: Read-only Reset: See Table 13 — — — — • WPVS: Write Protect Violation Status Write Protect Violation ...
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SAM9G35 SAM9G35 110 110 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ...
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Reset Controller (RSTC) 14.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the sys- tem without any external components. It reports which reset occurred last. The Reset Controller also drives independently or ...
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Block Diagram Figure 14-1. Reset Controller Block Diagram Main Supply Backup Supply 14.4 Functional Description 14.4.1 Reset Controller Overview The Reset Controller is made NRST Manager, a Startup Counter and a Reset State Manager. It runs ...
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NRST Manager After power-up, NRST is an output during the ERSTL time defined in the RSTC. When ERSTL elapsed, the pin behaves as an input and all the system is held in reset if NRST is tied to GND ...
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Figure 14-3. BMS Sampling SLCK Core Supply POR output BMS Signal proc_nreset 14.4.5 Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of ...
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Figure 14-4. General Reset State SLCK MCK Backup Supply POR output Main Supply POR output backup_nreset proc_nreset RSTTYP periph_nreset NRST (nrst_out) 14.4.5.2 Wake-up Reset The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output ...
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Figure 14-5. Wake-up Reset SLCK MCK Main Supply POR output backup_nreset proc_nreset RSTTYP periph_nreset NRST (nrst_out) 14.4.5.3 User Reset The User Reset is entered when a low level is detected on the NRST pin. When a falling edge occurs on ...
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Figure 14-6. User Reset State SLCK Any MCK Freq. NRST proc_nreset RSTTYP Any periph_nreset NRST (nrst_out) 14.4.5.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control ...
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As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Prog- ress) is set in the Status Register (RSTC_SR cleared as soon as the software reset is left. No other software reset can ...
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Figure 14-8. Watchdog Reset SLCK MCK wd_fault proc_nreset RSTTYP periph_nreset Only if WDRPROC = 0 NRST (nrst_out) 14.4.6 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: • Backup ...
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Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: • RSTTYP field: This field gives the type of the last reset, as explained in previous sections. • SRCMP bit: This field indicates that a ...
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Reset Controller (RSTC) User Interface Table 14-1. Register Mapping Offset Register 0x00 Control Register 0x04 Status Register 0x08 Mode Register Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last ...
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Reset Controller Control Register Name: RSTC_CR Address: 0xFFFFFE00 Access : Write-only – – – – – – • PROCRST: Processor Reset effect KEY is correct, ...
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Reset Controller Status Register Name: RSTC_SR Address: 0xFFFFFE04 Access: Read-only 31 30 – – – – – – – – • URSTS: User Reset Status high-to-low edge on NRST happened ...
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Reset Controller Mode Register Name: RSTC_MR Address: 0xFFFFFE08 Access: Read-write – – – – – – • ERSTL: External Reset Length This field defines the external reset length. The external reset ...
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Periodic Interval Timer (PIT) 15.1 Description The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt designed to offer maximum accuracy and efficient management, even for systems with long response time. 15.2 Embedded Characteristics • 20-bit ...
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Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature built around two counters: a 20-bit CPIV counter and a ...
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Figure 15-2. Enabling/Disabling PIT with PITEN 15 MCK Prescaler 0 PITEN CPIV 0 PICNT PITS (PIT_SR) APB Interface 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 MCK 1 PIV - 1 PIV 1 0 read PIT_PIVR APB cycle APB cycle restarts MCK Prescaler 0 0 SAM9G35 ...
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Periodic Interval Timer (PIT) User Interface Table 15-1. Register Mapping Offset Register 0x00 Mode Register 0x04 Status Register 0x08 Periodic Interval Value Register 0x0C Periodic Interval Image Register SAM9G35 SAM9G35 128 128 Name Access PIT_MR Read-write PIT_SR Read-only PIT_PIVR ...
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Periodic Interval Timer Mode Register Name: PIT_MR Address: 0xFFFFFE30 Access: Read-write 31 30 – – – – • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the ...
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Periodic Interval Timer Status Register Name: PIT_SR Address: 0xFFFFFE34 Access: Read-only 31 30 – – – – – – – – • PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer ...
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Periodic Interval Timer Value Register Name: PIT_PIVR Address: 0xFFFFFE38 Access: Read-only PICNT Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the ...
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Periodic Interval Timer Image Register Name: PIT_PIIR Address: 0xFFFFFE3C Access: Read-only PICNT • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval ...
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Real-time Clock (RTC) 16.1 Description The Real-time Clock (RTC) peripheral is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian calen- dar, complemented by a programmable periodic interrupt. The alarm ...
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Product Dependencies 16.4.1 Power Management The Real-time Clock is continuously clocked at 32768 Hz. The Power Management Controller has no effect on RTC behavior. 16.4.2 Interrupt Within the System Controller, the RTC interrupt is OR-wired with all the other ...
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If only the “seconds” field is enabled, then an alarm is generated every minute. Depending on the combination of fields enabled, a large number of possibilities are available to the user ranging from minutes to 365/366 days. 16.5.4 Error ...
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Figure 16-2. Update Sequence SAM9G35 SAM9G35 136 136 Begin Prepare TIme or Calendar Fields Set UPDTIM and/or UPDCAL bit(s) in RTC_CR Read RTC_SR No ACKUPD = 1 ? Yes Clear ACKUPD bit in RTC_SCCR Update Time and/or Calendar values in ...
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Real Time Clock (RTC) User Interface Table 16-1. Register Mapping Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Time Register 0x0C Calendar Register 0x10 Time Alarm Register 0x14 Calendar Alarm Register 0x18 Status Register 0x1C Status Clear Command ...
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RTC Control Register Name: RTC_CR Address: 0xFFFFFEB0 Access: Read-write 31 30 – – – – – – – – • UPDTIM: Update Request Time Register effect Stops the ...
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RTC Mode Register Name: RTC_MR Address: 0xFFFFFEB4 Access: Read-write 31 30 – – – – – – – – • HRMOD: 12-/24-hour Mode 0 = 24-hour mode is selected 12-hour mode ...
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RTC Time Register Name: RTC_TIMR Address: 0xFFFFFEB8 Access: Read-write 31 30 – – – AMPM 15 14 – – • SEC: Current Second The range that can be set (BCD). The ...
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RTC Calendar Register Name: RTC_CALR Address: 0xFFFFFEBC Access: Read-write 31 30 – – DAY – • CENT: Current Century The range that can be set (BCD). The lowest four ...
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RTC Time Alarm Register Name: RTC_TIMALR Address: 0xFFFFFEC0 Access: Read-write 31 30 – – HOUREN AMPM 15 14 MINEN 7 6 SECEN • SEC: Second Alarm This field is the alarm field corresponding to the BCD-coded second ...
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RTC Calendar Alarm Register Name: RTC_CALALR Address: 0xFFFFFEC4 Access: Read-write 31 30 DATEEN – MTHEN – – – – – • MONTH: Month Alarm This field is the alarm field corresponding to the ...
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RTC Status Register Name: RTC_SR Address: 0xFFFFFEC8 Access: Read-only 31 30 – – – – – – – – • ACKUPD: Acknowledge for Update 0 = Time and calendar registers cannot be updated. ...
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RTC Status Clear Command Register Name: RTC_SCCR Address: 0xFFFFFECC Access: Write-only 31 30 – – – – – – – – • ACKCLR: Acknowledge Clear effect Clears corresponding ...
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RTC Interrupt Enable Register Name: RTC_IER Address: 0xFFFFFED0 Access: Write-only 31 30 – – – – – – – – • ACKEN: Acknowledge Update Interrupt Enable effect The ...
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RTC Interrupt Disable Register Name: RTC_IDR Address: 0xFFFFFED4 Access: Write-only 31 30 – – – – – – – – • ACKDIS: Acknowledge Update Interrupt Disable effect The ...
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RTC Interrupt Mask Register Name: RTC_IMR Address: 0xFFFFFED8 Access: Read-only 31 30 – – – – – – – – • ACK: Acknowledge Update Interrupt Mask 0 = The acknowledge for update interrupt ...
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RTC Valid Entry Register Name: RTC_VER Address: 0xFFFFFEDC Access: Read-only 31 30 – – – – – – – – • NVTIM: Non-valid Time invalid data has been detected in ...
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SAM9G35 SAM9G35 150 150 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ...
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Watchdog Timer (WDT) 17.1 Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period seconds ...
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Functional Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock supplied with VDDCORE. It restarts with initial values on processor reset. The Watchdog is built around a ...
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While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR. Figure 17-2. Watchdog Behavior FFF Normal behavior WDV Forbidden Window ...
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Watchdog Timer (WDT) User Interface Table 17-1. Register Mapping Offset Register 0x00 Control Register 0x04 Mode Register 0x08 Status Register SAM9G35 SAM9G35 154 154 Name Access WDT_CR Write-only WDT_MR Read-write Once WDT_SR Read-only Reset - 0x3FFF_2FFF 0x0000_0000 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ...
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Watchdog Timer Control Register Name: WDT_CR Address: 0xFFFFFE40 Access: Write-only – – – – – – • WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. • KEY: Password Should ...
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Watchdog Timer Mode Register Name: WDT_MR Address: 0xFFFFFE44 Access: Read-write Once 31 30 WDIDLEHLT WDDIS WDRPROC WDRSTEN 7 6 • WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. • WDFIEN: ...
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Enables the Watchdog Timer. 1: Disables the Watchdog Timer. SAM9G35 SAM9G35 157 157 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ...
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Watchdog Timer Status Register Name: WDT_SR Address: 0xFFFFFE48 Access: Read-only 31 30 – – – – – – – – • WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read ...
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Shutdown Controller (SHDWC) 18.1 Description The Shutdown Controller controls the power supplies VDDIO and VDDCORE and the wake-up detection on debounced input lines. 18.2 Embedded Characteristics • Shutdown and Wake-up Logic – Software Assertion of the SHDW Output Pin ...
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Figure 18-2. Shutdown Controller Block Diagram Shutdown Controller SHDW_MR CPTWK0 WKMODE0 WKUP0 RTTWKEN RTC Alarm 18.4 I/O Lines Description Table 18-1. I/O Lines Description Name Description WKUP0 Wake-up 0 input SHDN Shutdown output 18.5 Product Dependencies 18.5.1 Power Management The ...
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As a result, the system should be powered down. A level change on WKUP0 is used as wake-up. Wake-up is configured in the Shutdown Mode Register (SHDW_MR). ...
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Shutdown Controller (SHDWC) User Interface Table 18-2. Register Mapping Offset Register 0x00 Shutdown Control Register 0x04 Shutdown Mode Register 0x08 Shutdown Status Register SAM9G35 SAM9G35 162 162 Name Access SHDW_CR Write-only SHDW_MR Read-write SHDW_SR Read-only Reset - 0x0000_0003 0x0000_0000 ...
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Shutdown Control Register Name: SHDW_CR Address: 0xFFFFFE10 Access: Write-only – – – – – – • SHDW: Shutdown Command effect KEY is correct, asserts the ...
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Shutdown Mode Register Name: SHDW_MR Address: 0xFFFFFE14 Access: Read/Write 31 30 – – – – – CPTWK0 • WKMODE0: Wake-up Mode 0 WKMODE[1:0] Wake-up Input Transition Selection 0 0 None. No detection is ...
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Shutdown Status Register Name: SHDW_SR Address: 0xFFFFFE18 Access: Read-only 31 30 – – – – – – – – • WAKEUP0: Wake-up 0 Status wake-up event occurred on the corresponding ...
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SAM9G35 SAM9G35 166 166 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 ...
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General Purpose Backup Registers (GPBR) 19.1 Description The System Controller embeds Four general-purpose backup registers. 19.2 Embedded Characteristics • Four 32-bit General Purpose Backup Registers 19.3 General Purpose Backup Registers (GPBR) User Interface Table 19-1. Register Mapping Offset Register ...
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General Purpose Backup Register x Name: SYS_GPBRx Address: 0xFFFFFE60 [0], 0xFFFFFE64 [1], 0xFFFFFE68 [2], 0xFFFFFE6C [3] Access: Read-write • GPBR_VALUEx: Value of GPBR x SAM9G35 SAM9G35 168 168 ...
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Slow Clock Controller (SCKC) 20.1 Description The System Controller embeds a Slow Clock Controller. The slow clock can be generated either by an external 32,768 Hz crystal oscillator or by the on- chip 32 kHz RC oscillator. The 32,768 ...
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Wait 32,768 Hz Startup Time for clock stabilization (software loop). • Switch from internal 32 kHz RC oscillator to 32,768 Hz oscillator by setting the bit OSCSEL to 1. • Wait 5 slow clock cycles for internal resynchronization. • ...
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Slow Clock Configuration (SCKC) User Interface Table 20-1. Register Mapping Offset Register 0x0 Slow Clock Configuration Register 11053B–ATARM–22-Sep-11 11053B–ATARM–22-Sep-11 Name Access SCKC_CR Read-write SAM9G35 SAM9G35 Reset 0x0000_0001 171 171 ...
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Slow Clock Configuration Register Name: SCKC_CR Address: 0xFFFFFE50 Access: Read-write Reset: 0x0000_0001 31 30 – – – – – – – – • RCEN: Internal 32 kHz RC Oscillator 0: 32 kHz RC ...
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Clock Generator (CKGR) 21.1 Description The Clock Generator User Interface is embedded within the Power Management Controller and is described in the Clock Generator registers are named CKGR_. 21.2 Embedded Characteristics The Clock Generator is made up of: • ...
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CKGR Block Diagram Figure 21-1. Clock Generator Block Diagram 21.4 Slow Clock Selection The slow clock can be generated either by an external 32,768 Hz crystal or by the on-chip 32 kHz RC oscillator. The 32,768 Hz crystal oscillator ...
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Figure 21-2. Slow Clock RCEN, OSC32EN,OSCSEL and OSC32BYP bits are located in the Slow Clock Control Register (SCKCR) located at address 0xFFFFFE50 in the backed up part of the System Controller and so are preserved while VDDBU is present. After ...
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Switch from the 32,768 Hz Crystal to Internal 32 kHz RC Oscillator The same procedure must be followed to switch from a 32,768 Hz crystal to the internal 32 kHz RC oscillator. • Switch the master clock to a ...
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Slow Clock Configuration Register Name: SCKCR Address: 0xFFFFFE50 Access: Read-write Reset Value: 0x0000_0001 31 30 – – – – – – – – • RCEN: Internal 32 kHz kHz RC ...
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Main Clock Figure 21-3. Main Clock Block Diagram The Main Clock has two sources: • 12 MHz Fast RC Oscillator which starts very quickly and is used at startup • MHz Crystal Oscillator, which can be ...
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Figure 21-4. Main Clock Selection MOSCRCEN, MOSCXTEN, MOSCSEL and MOSCXTBY bits are located in the PMC Clock Generator Main Oscillator Register (CKGR_MOR). After a VDDBU power on reset, the default configuration is MOSCRCEN = 1, MOSCXTEN = 0 and MOSCSEL ...
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Switch from Internal 12 MHz RC Oscillator to the 12 MHz Crystal For USB operations an external 12 MHz crystal is required for better accuracy. The programmer controls the main clock switching by software and so must take precautions ...
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The user can select the MHz crystal oscillator to be the source of MAINCK provides a more accurate frequency. The software enables or disables the main oscillator reduce power consumption by clearing ...
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Slow Clock, so that the frequency of the 12 MHz Fast RC Oscillator MHz Crystal Oscillator can be determined. 21.7 Divider and PLLA Block The PLLA embeds an input divider to increase the ...
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Figure 21-7. UTMI PLL Block Diagram Whenever the UTMI PLL is enabled by writing UPLLEN in CKGR_UCKR, the LOCKU bit in PMC_SR is automatically cleared. The values written in the PLLCOUNT field in CKGR_UCKR are loaded in the UTMI PLL ...
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Power Management Controller (PMC) 22.1 Description The Power Management Controller (PMC) optimizes power consumption by controlling all sys- tem and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Core. 22.2 Embedded ...
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Master Clock Controller The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided to all the peripherals and the memory controller. The Master Clock is selected from one of the clocks ...
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Block Diagram Figure 22-2. General Clock Block Diagram PLLACK /1,/2 UPLLCK 22.5 Processor Clock Controller The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle Mode. The Processor Clock can be disabled by writing the System ...
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USB Device and Host Clocks The USB Device and Host High Speed ports clocks are controlled by the UDPHS and UHPHS bits in PMC_PCER. To save power on this peripheral when they are is not used, the user can ...
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Code Example to select divider 8 for peripheral 2 and enable its clock: write_register(PMC_PCR,0x010031002) Code Example to read the divider of peripheral 4: write_register(PMC_PCR,0x00000004) read_register(PMC_PCR) When a peripheral clock is disabled, the clock is immediately stopped. The peripheral clocks are ...
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All parameters needed to configure PLLA and the divider are located in the CKGR_PLLAR register. The DIVA field is used to control the divider itself. A value between 0 and 255 can be pro- grammed. Divider output is divider input ...
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PRES parameter. By default, PRES parameter is set to 1 which means that the input clock of the Master Clock and Processor Clock dividers is equal to slow clock. The MDIV field is used to control ...
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The Processor Clock is the Master Clock. 5. Selection of Programmable clocks Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and PMC_SCSR. Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDR registers. Depending on the system used, ...
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Clock Switching Details 22.12.1 Master Clock Switching Timings Table 22-1 from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles ...
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Clock Switching Waveforms Figure 22-3. Switch Master Clock from Slow Clock to PLL Clock Write PMC_MCKR Figure 22-4. Switch Master Clock from Main Clock to Slow Clock Write PMC_MCKR 11053B–ATARM–22-Sep-11 Slow Clock PLL Clock LOCK MCKRDY Master Clock Slow ...
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Figure 22-5. Change PLLA Programming Write CKGR_PLLAR Figure 22-6. Programmable Clock Output Programming Write PMC_PCKx Write PMC_SCER Write PMC_SCDR SAM9G35 194 Slow Clock PLLA Clock LOCKA MCKRDY Master Clock PLL Clock PCKRDY PCKx Output PLL Clock is selected Slow Clock ...
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Power Management Controller (PMC) User Interface Table 22-3. Register Mapping Offset Register 0x0000 System Clock Enable Register 0x0004 System Clock Disable Register 0x0008 System Clock Status Register 0x0010 Peripheral Clock Enable Register 0x0014 Peripheral Clock Disable Register 0x0018 Peripheral ...
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PMC System Clock Enable Register Name: PMC_SCER Access: Write-only 31 30 – – – – – – UDP UHP • DDRCK: DDR Clock Enable effect Enables the DDR ...
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PMC System Clock Disable Register Name: PMC_SCDR Access: Write-only 31 30 – – – – – – UDP UHP • PCK: Processor Clock Disable effect Disables the Processor ...
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PMC System Clock Status Register Name: PMC_SCSR Access: Read-only 31 30 – – – – – – UDP UHP • PCK: Processor Clock Status 0 = The Processor clock is disabled ...
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PMC Peripheral Clock Enable Register Name: PMC_PCER Access: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • PIDx: Peripheral Clock x Enable effect Enables the ...
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PMC Peripheral Clock Disable Register Name: PMC_PCDR Access: Write-only 31 30 PID31 PID30 23 22 PID23 PID22 15 14 PID15 PID14 7 6 PID7 PID6 • PIDx: Peripheral Clock x Disable effect Disables the ...