SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 116
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SAM9G10
Manufacturer Part Number
SAM9G10
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(1274 pages)
2.SAM9261.pdf
(43 pages)
3.SAM9G10.pdf
(750 pages)
4.SAM9G10.pdf
(39 pages)
Specifications of SAM9G10
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
266 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Figure 14-5. Wake-up Reset
14.4.5.3
116
116
SAM9G35
SAM9G35
backup_nreset
periph_nreset
User Reset
Main Supply
POR output
proc_nreset
(nrst_out)
RSTTYP
SLCK
NRST
MCK
The User Reset is entered when a low level is detected on the NRST pin. When a falling edge
occurs on NRST (reset activation), internal reset lines are immediately asserted.
The Processor Reset and the Peripheral Reset are asserted.
The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle
processor startup. The processor clock is re-enabled as soon as NRST is confirmed high.
When the processor reset signal is released, the RSTTYP field of the Status Register
(RSTC_SR) is loaded with the value 0x4, indicating a User Reset.
T h e
EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. How-
ever, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low
externally, the internal reset lines remain asserted until NRST actually rises.
N R S T
Resynch.
2 cycles
M a n a g e r
Processor Startup
XXX
EXTERNAL RESET LENGTH
= 4 cycles (ERSTL = 1)
g u a r a n t e e s
t h a t
0x1 = WakeUp Reset
t h e
N R S T
Freq.
Any
l i n e
i s
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
XXX
a s s e r t e d
f o r
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