SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 319

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

26.4.3
26.5
26.5.1
26.5.1.1
11053B–ATARM–22-Sep-11
Arbitration
Fixed Default Master
Arbitration Scheduling
Undefined Length Burst Arbitration
This configuration provides no benefit on access latency or bandwidth when reaching maximum
slave bus throughput irregardless of the number of requesting masters.
After the end of the current access, if no other request is pending, the slave connects to its fixed
default master. Unlike the last access master, the fixed default master does not change unless
the user modifies it by software (FIXED_DEFMSTR field of the related MATRIX_SCFG).
This allows the Bus Matrix arbiters to remove the one latency clock cycle for the fixed default
master of the slave. All requests attempted by the fixed default master do not cause any arbitra-
tion latency, whereas other non-privileged masters will get one latency cycle. This technique is
useful for a master that mainly performs single accesses or short bursts with Idle cycles in
between.
This configuration provides no benefit on access latency or bandwidth when reaching maximum
slave bus throughput, irregardless of the number of requesting masters.
The Bus Matrix provides an arbitration mechanism that reduces latency when conflict cases
occur, i.e. when two or more masters try to access the same slave at the same time. One arbiter
per AHB slave is provided, thus arbitrating each slave specifically.
The Bus Matrix provides the user with the possibility of choosing between 2 arbitration types or
mixing them for each slave:
The resulting algorithm may be complemented by selecting a default master configuration for
each slave.
When re-arbitration must be done, specific conditions apply. See
Scheduling”.
Each arbiter has the ability to arbitrate between two or more different master requests. In order
to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitra-
tion may only take place during the following cycles:
In order to prevent long AHB burst lengths that can lock the access to the slave for an excessive
period of time, the user can trigger the re-arbitration before the end of the incremental bursts.
1. Round-robin Arbitration (default)
2. Fixed Priority Arbitration
1. Idle Cycles: When a slave is not connected to any master or is connected to a master
2. Single Cycles: When a slave is currently doing a single access.
3. End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For
4. Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that
which is not currently accessing it.
defined length burst, predicted end of burst matches the size of the transfer but is man-
aged differently for undefined length burst. See
Burst Arbitration”
the current master access is too long and must be broken. See
Cycle Limit Arbitration”
Section 26.5.1.1 “Undefined Length
Section 26.5.1 “Arbitration
Section 26.5.1.2 “Slot
SAM9G35
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