SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 1241
SAM9G10
Manufacturer Part Number
SAM9G10
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(1274 pages)
2.SAM9261.pdf
(43 pages)
3.SAM9G10.pdf
(750 pages)
4.SAM9G10.pdf
(39 pages)
Specifications of SAM9G10
Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
266 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
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Figure 46-5. SMC Timings - NRD Controlled Read and NWE Controlled Write
46.16 DDRSDRC Timings
46.17 Peripheral Timings
46.17.1
46.17.1.1
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Master Write Mode
Master Read Mode
A0/A1/NBS[3:0]
D0 - D31
/A2-A25
NWE
NCS
NRD
SPI
Maximum SPI Frequency
SMC6
SMC5
NRD Controlled READ
The DDRSDRC controller satisfies the timings of standard DDR2, LP-DDR, SDR and LP-SDR
modules.
DDR2, LP-DDR and SDR timings are specified by the JEDEC standard.
Supported speed grade limitations:
The following formulas give maximum SPI frequency in Master read and write modes and in
Slave read and write modes.
with NO HOLD
SMC7
• DDR2-400 limited at 133MHz clock frequency (1.8V, 30pF on data/control, 10pF on CK/CK#)
• LP-DDR limited at 133MHz clock frequency (1.8V, 30pF on data/control, 10pF on CK)
• SDR-100 (3.3V, 50pF on data/control, 10pF on CK)
• SDR-133 (3.3V, 50pF on data/control, 10pF on CK)
• LP-SDR-133 (1.8V, 30pF on data/control, 10pF on CK)
The SPI is only sending data to a slave device such as an LCD, for example. The limit is
given by SPI
speed (see
T
DataFlash (AT45DB642D), T
This gives, F
f
SPCK
valid
SMC1
is the slave time response to output data after deleting an SPCK edge. For Atmel SPI
Max
SMC2
=
SMC17
Section 46.10
SMC18
2
SPCK
NWE Controlled WRITE
--------------------------------------------------------
SPI
(or SPI
with NO HOLD
Max = 39 MHz @ VDDIO = 3.3V.
0
SMC16
orSPI
SMC15
5
) timing. Since it gives a maximum frequency above the maximum pad
1
SMC21
SMC21
3
SMC21
“I/Os”), the max SPI frequency is the one from the pad.
+
SMC6
valid
T
SMC5
valid
(orT
NRD Controlled READ
v
SMC7
) is 12 ns Max.
with HOLD
SMC3
SMC4
SMC17
SMC18
NWE Controlled WRITE
with HOLD
SMC16
SMC15
SAM9G35
SAM9G35
SMC19
SMC20
SMC19
1241
1241
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