SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 624

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

34.8.6.2
624
624
SAM9G35
SAM9G35
Block Length is Not Multiple of 4 and Padding Not Used (ROPT field in HSMCI_DMA register set to 0)
In the previous DMA transfer flow (block length multiple of 4), the DMA controller is configured to
use only WORD AHB access. When the block length is no longer a multiple of 4 this is no longer
true. The DMA controller is programmed to copy exactly the block length number of bytes using
2 transfer descriptors.
8. Wait for XFRDONE in HSMCI_SR register.
1. Use the previous step until READ_SINGLE_BLOCK then
2. Program the DMA controller to use a two descriptors linked list.
a. Read the channel Register to choose an available (disabled) channel.
b. Clear any pending interrupts on the channel from the previous DMA transfer by
c. Program the channel registers in the Memory for the first descriptor. This descriptor
d. The LLI_W.DMAC_SADDRx field in memory must be set with the starting address
e. The LLI_W.DMAC_DADDRx field in the memory must be word aligned.
f.
g. Program LLI_W.DMAC_CTRLBx with the following field’s values:
h. Program LLI_W.DMAC_CFGx register for channel x with the following field’s
i.
–Enable Channel x, writing one to DMAC_CHER[x]. The DMAC is ready and
reading the DMAC_EBCISR register.
will be word oriented. This descriptor is referred to as LLI_W, standing for LLI word
oriented transfer.
of the HSMCI_FIFO address.
Program LLI_W.DMAC_CTRLAx with the following field’s values:
–DST_WIDTH is set to WORD.
–SRC_WIDTH is set to WORD.
–SCSIZE must be set according to the value of HSMCI_DMA, CHKSIZE field.
–BTSIZE is programmed with block_length/4. If BTSIZE is zero, this descriptor is
–DST_INCR is set to INCR
–SRC_INCR is set to INCR
–FC field is programmed with peripheral to memory flow control mode.
–SRC_DSCR is set to zero. (descriptor fetch is enabled for the SRC)
–DST_DSCR is set to one. (descriptor fetch is disabled for the DST)
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, DMA
values:
–FIFOCFG defines the watermark of the DMA channel FIFO.
–DST_REP is set to zero meaning that address are contiguous.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted
DSCRx_IF to the AHB Layer ID. This operation actually links the Word oriented
Program LLI_W.DMAC_DSCRx with the address of LLI_B descriptor. And set
waiting for request.
skipped later.
controller is able to prefetch data and write HSMCI simultaneously.
HSMCI Host Controller.
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11