SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 447

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 30-22. Power-down Entry/Exit, Timeout = 0
30.5.4.3
Figure 30-23. Deep Power-down Mode Entry
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
COMMAND
DQS[1:0]
DM[1:0]
SDCLK
BA[1:0]
D[15:0]
A[12:0]
COMMAND
CKE
Deep Power-down Mode
DQS[1:0]
DM[1:0]
SDCLK
BA[1:0]
A[12:0]
D[15:0]
CKE
NOP READ
0
3
0
3
READ
The deep power-down mode is a new feature of the Low-power SDRAM. When this mode is
activated, all internal voltage generators inside the device are stopped and all data is lost.
This mode is activated by setting the low-power command bits [LPCB] to ‘11’. When this mode is
enabled, the DDRSDRC leaves normal mode (mode == 000) and the controller is frozen. To exit
deep power-down mode, the low-power bits (LPCB) must be set to “00”, an initialization
sequence must be generated by software. See
tialization” on page
BST
BST
NOP
NOP
Da
429.
Da
Db
Db
Entry power down mode
Section 30.4.2 “Low-power DDR1-SDRAM Ini-
PRCHG
NOP
Exit power down mode
Trp
DEEPOWER
READ
Enter Deep
Power-down
Mode
SAM9G35
SAM9G35
NOP
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