SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 113

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

14.4.2
14.4.3
14.4.3.1
14.4.4
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
NRST Manager
NRST Signal
BMS Sampling
NRST External Reset Control
After power-up, NRST is an output during the ERSTL time defined in the RSTC. When ERSTL
elapsed, the pin behaves as an input and all the system is held in reset if NRST is tied to GND
by an external signal.
The NRST Manager samples the NRST input pin and drives this pin low when required by the
Reset State Manager.
Figure 14-2. NRST Manager
The NRST Manager handles the NRST input line asynchronously. When the line is low, a User
Reset is immediately reported to the Reset State Manager. When the NRST goes from low to
high, the internal reset is synchronized with the Slow Clock to provide a safe internal de-asser-
tion of reset.
The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR.
As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only
when RSTC_SR is read.
The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this
occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the
field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts
2
and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.
This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that
the NRST line is driven low for a time compliant with potential external devices connected on the
system reset.
As the field is within RSTC_MR, which is backed-up, this field can be used to shape the system
power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator.
The product matrix manages a boot memory that depends on the level on the BMS pin at reset.
The BMS signal is sampled three slow clock cycles after the Core Power-On-Reset output rising
edge.
(ERSTL+1)
Slow Clock cycles. This gives the approximate duration of an assertion between 60 μs
NRST
Figure 14-2
RSTC_SR
nrst_out
URSTS
NRSTL
shows the block diagram of the NRST Manager.
RSTC_MR
External Reset Timer
ERSTL
user_reset
exter_nreset
SAM9G35
SAM9G35
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