SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 634

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

34.10.2
34.10.3
34.10.4
634
634
SAM9G35
SAM9G35
Executing an ATA Interrupt Command
Aborting an ATA Command
CE-ATA Error Recovery
If the host needs to abort an ATA command prior to the completion signal it must send a special
command to avoid potential collision on the command line. The SPCMD field of the
HSMCI_CMDR must be set to 3 to issue the CE-ATA completion Signal Disable Command.
Several methods of ATA command failure may occur, including:
Error conditions are expected to happen infrequently. Thus, a robust error recovery mechanism
may be used for each error event. The recommended error recovery procedure after a timeout
is:
If STOP_TRANMISSION (CMD12) is successful, then the device is again ready for ATA com-
mands. However, if the error recovery procedure does not work as expected or there is another
timeout, the next step is to issue GO_IDLE_STATE (CMD0) to the device. GO_IDLE_STATE
(CMD0) is a hard reset to the device and completely resets all device states.
Note that after issuing GO_IDLE_STATE (CMD0), all device initialization needs to be completed
again. If the CE-ATA device completes all MMC commands correctly but fails the ATA command
with the ERR bit set in the ATA Status register, no error recovery action is required. The ATA
command itself failed implying that the device could not complete the action requested, how-
ever, there was no communication or protocol failure. After the device signals an error by setting
the ERR bit to one in the ATA Status register, the host may attempt to retry the command.
3. Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA.
4. Read the ATA status register until DRQ && BSY are set to 0.
1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for 8kB of DATA
2. Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA.
3. Wait for Completion Signal Received Interrupt.
• No response to an MMC command, such as RW_MULTIPLE_REGISTER (CMD60).
• CRC is invalid for an MMC command or response.
• CRC16 is invalid for an MMC data packet.
• ATA Status register reflects an error by setting the ERR bit to one.
• The command completion signal does not arrive within a host specified time out period.
• Issue the command completion signal disable if nIEN was cleared to zero and the
• Issue STOP_TRANSMISSION (CMD12) and successfully receive the R1 response.
• Issue a software reset to the CE-ATA device using FAST_IO (CMD39).
RW_MULTIPLE_BLOCK (CMD61) response has been received.
with nIEN field set to zero to enable the command completion signal in the device.
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11