SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 396

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 29-16. Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2
29.10.2
396
396
SAM9G35
SAM9G35
Early Read Wait State
NBS0, NBS1,
NBS2, NBS3,
A0,A1
A[25:2]
D[31:0]
NCS0
NCS2
NWE
MCK
NRD
Figure 29-16
Select 2.
In some cases, the SMC inserts a wait state cycle between a write access and a read access to
allow time for the write cycle to end before the subsequent read cycle begins. This wait state is
not generated in addition to a chip select wait state. The early read cycle thus only occurs
between a write and read access to the same memory device (same chip select).
An early read wait state is automatically inserted if at least one of the following conditions is
valid:
• if the write controlling signal has no hold time and the read controlling signal has no setup
• in NCS write controlled mode (WRITE_MODE = 0), if there is no hold timing on the NCS
• in NWE controlled mode (WRITE_MODE = 1) and if there is no hold timing (NWE_HOLD =
time
signal and the NCS_RD_SETUP parameter is set to 0, regardless of the read mode
29-18). The write operation must end with a NCS rising edge. Without an Early Read Wait
State, the write operation could not complete properly.
0), the feedback of the write control signal is used to control address, data, chip select and
byte select lines. If the external write control signal is not inactivated as expected due to load
capacitances, an Early Read Wait State is inserted and address, data and control signals are
maintained one more cycle. See
(Figure
NRD_CYCLE
illustrates a chip select wait state between access on Chip Select 0 and Chip
29-17).
Read to Write
Wait State
Figure
29-19.
Chip Select
Wait State
NWE_CYCLE
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
(Figure