SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 320

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

26.5.1.2
320
SAM9G35
Slot Cycle Limit Arbitration
The re-arbitration period can be selected from the following Undefined Length Burst Type
(ULBT) possibilities:
Use of undefined length16-beat bursts, or less, is discouraged since this generally decreases
significantly overall bus bandwidth due to arbitration and slave latencies at each first access of a
burst.
If the master does not permanently and continuously request the same slave or has an intrinsi-
cally limited average throughput, the ULBT should be left at its default unlimited value, knowing
that the AHB specification natively limits all word bursts to 256 beats and double-word bursts to
128 beats because of its 1 Kilobyte address boundaries.
Unless duly needed, the ULBT should be left at its default value of 0 for power saving.
This selection can be done through the ULBT field of the Master Configuration Registers
(MATRIX_MCFG).
The Bus Matrix contains specific logic to break long accesses, such as back-to-back undefined
length bursts or very long bursts on a very slow slave (e.g., an external low speed memory). At
each arbitration time a counter is loaded with the value previously written in the SLOT_CYCLE
field of the related Slave Configuration Register (MATRIX_SCFG) and decreased at each clock
cycle. When the counter elapses, the arbiter has the ability to re-arbitrate at the end of the cur-
rent AHB bus access cycle.
Unless a master has a very tight access latency constraint, which could lead to data overflow or
underflow due to a badly undersized internal FIFO with respect to its throughput, the Slot Cycle
Limit should be disabled (SLOT_CYCLE = 0) or set to its default maximum value in order not to
inefficiently break long bursts performed by some Atmel masters.
However, the Slot Cycle Limit should not be disabled in the particular case of a master capable
of accessing the slave by performing back-to-back undefined length bursts shorter than the
number of ULBT beats with no Idle cycle in between, since in this case the arbitration could be
frozen all along the burst sequence.
In most cases this feature is not needed and should be disabled for power saving.
1. Unlimited: no predetermined end of burst is generated. This value enables 1-kbyte
2. 1-beat bursts: predetermined end of burst is generated at each single transfer during
3. 4-beat bursts: predetermined end of burst is generated at the end of each 4-beat
4. 8-beat bursts: predetermined end of burst is generated at the end of each 8-beat
5. 16-beat bursts: predetermined end of burst is generated at the end of each 16-beat
6. 32-beat bursts: predetermined end of burst is generated at the end of each 32-beat
7. 64-beat bursts: predetermined end of burst is generated at the end of each 64-beat
8. 128-beat bursts: predetermined end of burst is generated at the end of each 128-beat
burst lengths.
the INCR transfer.
boundary during INCR transfer.
boundary during INCR transfer.
boundary during INCR transfer.
boundary during INCR transfer.
boundary during INCR transfer.
boundary during INCR transfer.
11053B–ATARM–22-Sep-11