SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 518

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SAM9G10

Manufacturer Part Number
SAM9G10
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G10

Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
266 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
31.7.13
Name:
Address:
Access:
Reset:
This register can only be written if the WPEN bit is cleared in
• SADDR: Channel x source address.
This register must be aligned with the source transfer width.
518
518
31
23
15
7
SAM9G35
SAM9G35
DMAC Channel x [x = 0..7] Source Address Register
0xFFFFEC3C (0)[0], 0xFFFFEC64 (0)[1], 0xFFFFEC8C (0)[2], 0xFFFFECB4 (0)[3], 0xFFFFECDC (0)[4],
0xFFFFED04 (0)[5], 0xFFFFED2C (0)[6], 0xFFFFED54 (0)[7], 0xFFFFEE3C (1)[0], 0xFFFFEE64 (1)[1],
0xFFFFEE8C (1)[2], 0xFFFFEEB4 (1)[3], 0xFFFFEEDC (1)[4], 0xFFFFEF04 (1)[5], 0xFFFFEF2C (1)[6],
0xFFFFEF54 (1)[7]
Read-write
0x00000000
DMAC_SADDRx [x = 0..7]
30
22
14
6
29
21
13
5
28
20
12
4
SADDR
SADDR
SADDR
SADDR
“DMAC Write Protect Mode Register”
27
19
11
3
26
18
10
2
25
17
9
1
.
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
24
16
8
0

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