SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 277

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 24-10. Character Transmission
24.5.3.3
Figure 24-11. Transmitter Control
24.5.4
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Shift Register
DBGU_THR
TXEMPTY
TXRDY
DTXD
DMA Support
in DBGU_THR
Write Data 0
Transmitter Control
Baud Rate
Example: Parity enabled
DTXD
Clock
S
Data 0
in DBGU_THR
PARE in the mode register DBGU_MR defines whether or not a parity bit is shifted out. When a
parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or
mark bit.
When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register
DBGU_SR. The transmission starts when the programmer writes in the Transmit Holding Regis-
ter DBGU_THR, and after the written character is transferred from DBGU_THR to the Shift
Register. The bit TXRDY remains high until a second character is written in DBGU_THR. As
soon as the first character is completed, the last character written in DBGU_THR is transferred
into the shift register and TXRDY rises again, showing that the holding register is empty.
When both the Shift Register and the DBGU_THR are empty, i.e., all the characters written in
DBGU_THR have been processed, the bit TXEMPTY rises after the last stop bit has been
completed.
Both the receiver and the transmitter of the Debug Unit’s UART are connected to a DMA Con-
troller (DMAC) channel.
The DMA Controller channels are programmed via registers that are mapped within the DMAC
user interface.
Write Data 1
Start
Bit
Data 0
D0
Data 0
D1
P
D2
stop
D3
S
D4
D5
Data 1
D6
Data 1
D7
Parity
Bit
P
Stop
Bit
Data 1
stop
SAM9G35
SAM9G35
277
277