SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 751

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SAM9G10

Manufacturer Part Number
SAM9G10
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of SAM9G10

Flash (kbytes)
0 Kbytes
Pin Count
217
Max. Operating Frequency
266 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
96
Ext Interrupts
96
Usb Transceiver
3
Usb Speed
Full Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
1
Uart
4
Ssc
3
Sd / Emmc
1
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
No
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
NO
External Bus Interface
1
Dram Memory
sdram
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.08 to 1.32
Fpu
No
Mpu / Mmu
No/Yes
Timers
3
Output Compare Channels
3
Input Capture Channels
3
32khz Rtc
Yes
Calibrated Rc Oscillator
No
37.7.9
Name:
Address:
Access:
• CPRE: Channel Pre-scaler
Values which are not listed in the table must be considered as “reserved”.
• CALG: Channel Alignment
0 = The period is left aligned.
1 = The period is center aligned.
• CPOL: Channel Polarity
0 = The output waveform starts at a low level.
1 = The output waveform starts at a high level.
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Value
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
31
23
15
7
PWM Channel Mode Register
Name
MCK
MCKDIV2
MCKDIV4
MCKDIV8
MCKDIV16
MCKDIV32
MCKDIV64
MCKDIV128
MCKDIV256
MCKDIV512
MCKDIV1024
CLKA
CLKB
30
22
14
6
PWM_CMR[0..3]
0xF8034200 [0], 0xF8034220 [1], 0xF8034240 [2], 0xF8034260 [3]
Read-write
Description
Master Clock
Master Clock divided by 2
Master Clock divided by 4
Master Clock divided by 8
Master Clock divided by 16
Master Clock divided by 32
Master Clock divided by 64
Master Clock divided by 128
Master Clock divided by 256
Master Clock divided by 512
Master Clock divided by 1024
Clock A
Clock B
29
21
13
5
28
20
12
4
27
19
11
3
CPD
26
18
10
2
CPRE
CPOL
25
17
9
1
SAM9G35
SAM9G35
CALG
24
16
8
0
751
751

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