SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 37

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

9.4.8
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
ARM Instruction Set Overview
The breakpoint (BKPT) instruction is a new feature of ARM9EJ-S that is destined to solve the
problem of the Prefetch Abort. A breakpoint instruction operates as though the instruction
caused a Prefetch Abort.
A breakpoint instruction does not cause the ARM9EJ-S to take the Prefetch Abort exception until
the instruction reaches the Execute stage of the pipeline. If the instruction is not executed, for
example because a branch occurs while it is in the pipeline, the breakpoint does not take place.
The ARM instruction set is divided into:
ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition
code field (bits[31:28]).
For further details, see the ARM Technical Reference Manual.
Table 9-2
Table 9-2.
Mnemonic
• Branch instructions
• Data processing instructions
• Status register transfer instructions
• Load and Store instructions
• Coprocessor instructions
• Exception-generating instructions
LDRSH
SMULL
SMLAL
LDRSB
LDRH
LDRB
MOV
CMP
MSR
ADD
SUB
RSB
AND
EOR
MUL
LDR
TST
BX
B
gives the ARM instruction mnemonic list.
ARM Instruction Mnemonic List
Operation
Move
Add
Subtract
Reverse Subtract
Compare
Test
Logical AND
Logical Exclusive OR
Multiply
Sign Long Multiply
Signed Long Multiply
Accumulate
Move to Status Register
Branch and Exchange
Load Word
Load Signed Halfword
Load Signed Byte
Load Half Word
Load Byte
Branch
Mnemonic
UMULL
UMLAL
STRH
STRB
MVN
CMN
ORR
MRS
ADC
SBC
RSC
TEQ
MLA
SWI
STR
BIC
BL
Operation
Move Not
Add with Carry
Subtract with Carry
Reverse Subtract with Carry
Compare Negated
Test Equivalence
Bit Clear
Logical (inclusive) OR
Multiply Accumulate
Unsigned Long Multiply
Unsigned Long Multiply
Accumulate
Move From Status Register
Branch and Link
Software Interrupt
Store Word
Store Half Word
Store Byte
SAM9G35
SAM9G35
37
37