SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 337

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

27.4
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Functional Description
The NAND Flash sector size is programmable and can be set to 512 bytes or 1024 bytes. The
PMECC module generates redundancy at encoding time, when a NAND write page operation is
performed. The redundancy is appended to the page and written in the spare area. This opera-
tion is performed by the processor. It moves the content of the PMECCx registers into the NAND
Flash memory. The number of registers depends on the selected error correction capability,
refer to
the PMECC module generates the remainder of the received codeword by minimal polynomials.
When all polynomial remainders for a given sector are set to zero, no error occurred. When the
polynomial remainders are other than zero, the codeword is corrupted and further processing is
required.
The PMECC module generates an interrupt indicating that an error occurred. The processor
must read the PMECCISR register. This register indicates which sector is corrupted.
To find the error location within a sector, the processor must execute the decoding steps as
follows:
All decoding steps involve finite field computation. It means that a library of finite field arithmetic
must be available to perform addition, multiplication and inversion. The finite field arithmetic
operations can be performed through the use of a memory mapped lookup table, or direct soft-
ware implementation. The software implementation presented is based on lookup tables. Two
tables named gf_log and gf_antilog are used. If alpha is the primitive element of the field, then a
power of alpha is in the field. Assume beta = alpha ^ index, then beta belongs to the field, and
gf_log(beta) = gf_log(alpha ^ index) = index. The gf_antilog tables provide exponent inverse of
the element, if beta = alpha ^ index, then gf_antilog(index) = beta.
The first step consists of the syndrome computation. The PMECC module computes the remain-
ders and software must substitute the power of the primitive element.
The procedure implementation is given in
page
The second step is the most software intensive. It is the Berlekamp’s iterative algorithm for find-
ing the error-location polynomial.
The procedure implementation is given in
Sigma(x)” on page
The Last step is finding the root of the error location polynomial. This step can be very software
intensive. Indeed, there is no straightforward method of finding the roots, except by evaluating
each element of the field in the error location polynomial. However a hardware accelerator can
be used to find the roots of the polynomial. The Programmable Multibit Error Correction Code
Location (PMERRLOC) module provides this kind of hardware acceleration.
1. Syndrome computation
2. Find the error locator polynomials
3. Find the roots of the error locator polynomial
343.
Table 27-1 on page
343.
339. This operation is executed for each sector. At decoding time,
Section 27.5.1 “Remainder Substitution Procedure” on
Section 27.5.2 “Find the Error Location Polynomial
SAM9G35
SAM9G35
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