SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 763

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 38-7. Master Write with Multiple Data Bytes
Figure 38-8. Master Write with One Byte Internal Address and Multiple Data Bytes
38.8.5
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
TXCOMP
TXRDY
TXCOMP
TWCK
TWD
TXRDY
TWCK
TWD
Write THR (Data n)
S
Master Receiver Mode
Write THR (Data n)
S
DADR
DADR
W
The read sequence begins by setting the START bit. After the start condition has been sent, the
master sends a 7-bit slave address to notify the slave device. The bit following the slave address
indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowl-
edge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data
has been received, the master sends an acknowledge condition to notify the slave that the data
has been received except for the last data, after the stop condition. See
W
A
A
IADR
DATA n
A
DATA n
A
A
Write THR (Data n+1)
Write THR (Data n+1)
DATA n+1
STOP command performed
(by writing in the TWI_CR)
Write THR (Data n+2)
DATA n+1
STOP command performed
Last data sent
(by writing in the TWI_CR)
Write THR (Data n+2)
Last data sent
A
A
DATA n+2
Figure
DATA n+2
SAM9G35
SAM9G35
38-9. When the
A
A
P
P
763
763