SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 679

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 35-10. Peripheral Deselection
35.7.3.10
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Write SPI_TDR
Write SPI_TDR
Write SPI_TDR
NPCS[0..3]
NPCS[0..3]
NPCS[0..3]
TDRE
TDRE
TDRE
Mode Fault Detection
A
A
A
SPI_TDR by the DMAC as well. This means that the SPI_TDR might not be reloaded in time to
keep the chip select line low. In this case the chip select line may toggle between data transfer
and according to some SPI Slave devices, the communication might get lost. The use of the
CSAAT bit might be needed.
Figure 35-10
A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven
by an external master on the NPCS0/NSS signal. In this case, multi-master configuration,
NPCS0, MOSI, MISO and SPCK pins must be configured in open drain (through the PIO control-
ler). When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read
and the SPI is automatically disabled until re-enabled by writing the SPIEN bit in the SPI_CR
(Control Register) at 1.
By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault
detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR).
DLYBCT
DLYBCT
DLYBCT
CSAAT = 0
DLYBCS
DLYBCS
DLYBCS
PCS = B
PCS=A
shows different peripheral deselction cases and the effect of the CSAAT bit.
PCS = A
A
B
A
A
A
A
DLYBCT
DLYBCT
DLYBCT
CSAAT = 1
DLYBCS
DLYBCS
PCS = B
PCS = A
A
A
PCS = A
DLYBCS
SAM9G35
SAM9G35
A
A
B
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679