SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 449

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 30-25. Anticipate Precharge/Active Command in Bank 2 during Read Access in Bank 1
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
COMMAND
DQS[1:0]
BA[1:0]
DM1:0]
D[15:0]
A[12:0]
SDClK
NOP
0
3
READ
1
the case of four simultaneous read accesses, when the four banks and associated rows are
open, the controller reads with a continuous flow and masks the cas latency for each different
access. To allow a continuous flow, the read command must be set at 2 or 3 cycles (cas latency)
before the end of current access. This requires that the scheme of arbitration changes since the
round-robin arbitration cannot be respected. If the controller anticipates a read access, and thus
before the end of current access a master with a high priority arises, then this master will not
serviced.
The arbitration mechanism reduces latency when conflicts occur, i.e., when two or more masters
try to access the SDRAM device at the same time.
The arbitration type is round-robin arbitration. This algorithm dispatches the requests from differ-
ent masters to the SDRAM device in a round-robin manner. If two or more master requests arise
at the same time, the master with the lowest number is serviced first, then the others are ser-
viced in a round-robin manner. To avoid burst breaking and to provide the maximum throughput
for the SDRAM device, arbitration may only take place during the following cycles:
1. Idle cycles: When no master is connected to the SDRAM device.
2. Single cycles: When a slave is currently doing a single access.
3. End of Burst cycles: When the current cycle is the last cycle of a burst transfer. For
4. Anticipated Access: When an anticipate read access is done while current access is
Anticipate command, Precharge/Active Bank 2
bursts of defined length, predicted end of burst matches the size of the transfer. For
bursts of undefined length, predicted end of burst is generated at the end of each four
beat boundary inside the INCR transfer.
not complete, the arbitration scheme can be changed if the anticipated access is not
the next access serviced by the arbitration scheme.
PRECH
Read access in Bank 1
2
Trp
NOP
Da
Db
ACT
Dc
Dd
READ
1
De
Df
Dg
Dh
NOP
Di
SAM9G35
SAM9G35
Dj
Dk
Dl
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