SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 597

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

• NAK_OUT: NAK OUT
This bit is set by hardware when a NAK handshake has been sent in response to an OUT or PING request from the Host.
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by EPT_CTL_DISx (disable endpoint).
• CURRENT_BANK/CONTROL_DIR: Current Bank/Control Direction
These bits are set by hardware to indicate the number of the current bank.
Note:
This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint).
0 = a Control Write is requested by the Host.
1 = a Control Read is requested by the Host.
Notes:
• BUSY_BANK_STA: Busy Bank Number
These bits are set by hardware to indicate the number of busy banks.
• BYTE_COUNT: UDPHS Byte Count
Byte count of a received data packet.
This field is incremented after each write into the endpoint (to prepare an IN transfer).
This field is decremented after each reading into the endpoint (OUT transfer).
This field is also updated at RX_BK_RDY flag clear with the next bank.
This field is also updated at TX_PK_RDY flag set with the next bank.
This field is reset by EPT_x of UDPHS_EPTRST register.
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Value
Value
IN endpoint: it indicates the number of busy banks filled by the user, ready for IN transfer.
OUT endpoint: it indicates the number of busy banks filled by OUT transaction from the Host.
– Current Bank: (all endpoints except Control endpoint)
– Control Direction: (for Control endpoint only)
0
1
2
0
1
2
The current bank is updated each time the user:
- Sets the TX Packet Ready bit to prepare the next IN transfer and to switch to the next bank.
- Clears the received OUT data bit to access the next bank.
1. This bit corresponds with the 7th bit of the bmRequestType (Byte 0 of the Setup Data).
2. This bit is updated after receiving new setup data.
Name
BANK0
BANK1
BANK2
Name
1BUSYBANK
2BUSYBANKS
3BUSYBANKS
Description
Bank 0 (or single bank)
Bank 1
Bank 2
Description
1 busy bank
2 busy banks
3 busy banks
SAM9G35
SAM9G35
597
597