SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 190

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

190
SAM9G35
Note:
• If a new value for CSS field corresponds to PLLA Clock,
• If a new value for CSS field corresponds to Main Clock or Slow Clock,
clock source divided by PRES parameter. By default, PRES parameter is set to 1 which
means that the input clock of the Master Clock and Processor Clock dividers is equal to slow
clock.
The MDIV field is used to control the Master Clock divider. It is possible to choose between
different values (0, 1, 2, 3). The Master Clock output is Master/Processor Clock Prescaler
output divided by 1, 2, 4 or 3, depending on the value programmed in MDIV.
The PLLADIV2 field is used to control the PLLA Clock divider. It is possible to choose
between different values (0, 1). The PMC PLLA Clock input is divided by 1 or 2, depending
on the value programmed in PLLADIV2.
By default, MDIV and PLLLADIV2 are set to 0, which indicates that Processor Clock is equal
to the Master Clock.
Once the PMC_MCKR register has been written, the user must wait for the MCKRDY bit to
be set in the PMC_SR register. This can be done either by polling the status register or by
waiting for the interrupt line to be raised if the associated interrupt to MCKRDY has been
enabled in the PMC_IER register.
The PMC_MCKR register must not be programmed in a single write operation. The pre-
ferred programming sequence for the PMC_MCKR register is as follows:
If at some stage one of the following parameters, CSS or PRES, is modified, the MCKRDY
bit will go low to indicate that the Master Clock and the Processor Clock are not ready yet.
The user must wait for MCKRDY bit to be set again before using the Master and Processor
Clocks.
Code Example:
The Master Clock is main clock divided by 16.
– Program the PRES field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
– Program the CSS field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
– Program the CSS field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
– Program the PRES field in the PMC_MCKR register.
– Wait for the MCKRDY bit to be set in the PMC_SR register.
write_register(PMC_MCKR,0x00000001)
wait (MCKRDY=1)
write_register(PMC_MCKR,0x00000011)
wait (MCKRDY=1)
IF PLLA clock was selected as the Master Clock and the user decides to modify it by writing in
CKGR_PLLAR, the MCKRDY flag will go low while PLLA is unlocked. Once PLLA is locked again,
LOCK goes high and MCKRDY is set.
While PLLA is unlocked, the Master Clock selection is automatically changed to Main Clock. For
further information, see
Section
22.12.2.
“Clock Switching Waveforms” on page
11053B–ATARM–22-Sep-11
193.