SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 38

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

9.4.9
9.4.10
38
38
SAM9G35
SAM9G35
New ARM Instruction Set
Thumb Instruction Set Overview
Table 9-2.
Table 9-3.
Notes:
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
Mnemonic
Mnemonic
• Branch instructions
• Data processing instructions
• Load and Store instructions
SMULWy
SMLAWy
SMLAxy
SMULxy
QDADD
QDSUB
LDRBT
SMLAL
BLX
QADD
QSUB
LDRT
SWP
MCR
LDM
LDC
CDP
BXJ
(1)
1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.
ARM Instruction Mnemonic List (Continued)
New ARM Instruction Mnemonic List
Operation
Load Register Byte with
Translation
Load Register with
Translation
Load Multiple
Swap Word
Move To Coprocessor
Load To Coprocessor
Coprocessor Data
Processing
Operation
Branch and exchange to
Java
Branch, Link and exchange
Signed Multiply Accumulate
16 * 16 bit
Signed Multiply Accumulate
Long
Signed Multiply Accumulate
32 * 16 bit
Signed Multiply 16 * 16 bit
Signed Multiply 32 * 16 bit
Saturated Add
Saturated Add with Double
Saturated subtract
Saturated Subtract with
double
Mnemonic
Mnemonic
STRBT
SWPB
MRRC
MCRR
MCR2
CDP2
STRD
LDRD
STRT
BKPT
STC2
LDC2
MRC
STM
STC
PLD
CLZ
Operation
Store Register Byte with
Translation
Store Register with
Translation
Store Multiple
Swap Byte
Move From Coprocessor
Store From Coprocessor
Operation
Move double from
coprocessor
Alternative move of ARM reg
to coprocessor
Move double to coprocessor
Alternative Coprocessor
Data Processing
Breakpoint
Soft Preload, Memory
prepare to load from address
Store Double
Alternative Store from
Coprocessor
Load Double
Coprocessor
Count Leading Zeroes
Alternative Load to
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11