SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 487

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Note:
Note:
5. Make sure that the LLI.DMAC_DSCRx register locations of all LLI entries in memory
6. Make sure that the LLI.DMAC_SADDRx/LLI.DMAC_DADDRx register locations of all
7. Make sure that the LLI.DMAC_CTRLAx.DONE field of the LLI.DMAC_CTRLAx register
8. If source picture-picture mode is enabled (DMAC_CTRLBx.SRC_PIP is enabled), pro-
9. If destination picture-in-picture is enabled (DMAC_CTRLBx.DST_PIP is enabled), pro-
10. Clear any pending interrupts on the channel from the previous DMAC transfer by read-
11. Program the DMAC_CTRLBx, DMAC_CFGx registers according to Row 4 as shown in
12. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first
13. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENABLE[n] bit, where n
14. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0).
15. Source and destination request single and chunk DMAC transactions to transfer the
16. Once the buffer of data is transferred, the DMAC_CTRLAx register is written out to sys-
17. The DMAC does not wait for the buffer interrupt to be cleared, but continues fetching
Row 1 of
list items.
(except the last) are non-zero and point to the base address of the next Linked List
Item.
LLI entries in memory point to the start source/destination buffer address preceding
that LLI fetch.
locations of all LLI entries in memory are cleared.
gram the DMAC_SPIPx register for channel x.
gram the DMAC_DPIPx register for channel x.
ing the status register: DMAC_EBCISR.
Table 31-3 on page
Linked List item.
is the channel number. The transfer is performed.
buffer of data (assuming non-memory peripheral). The DMAC acknowledges at the
completion of every transaction (chunk and single) in the buffer and carry out the buffer
transfer.
tem memory at the same location and on the same layer (DMAC_DSCRx.DSCR_IF)
where it was originally fetched, that is, the location of the DMAC_CTRLAx register of
the linked list item fetched prior to the start of the buffer transfer. Only DMAC_CTRLAx
register is written out because only the DMAC_CTRLAx.BTSIZE and
DMAC_CTRLAX.DONE bits have been updated by DMAC hardware. Additionally, the
DMAC_CTRLAx.DONE bit is asserted when the buffer transfer has completed.
the next LLI from the memory location pointed to by current DMAC_DSCRx register
and automatically reprograms the DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx,
DMAC_CTRLAx and DMAC_CTRLBx channel registers. The DMAC transfer continues
until the DMAC determines that the DMAC_CTRLBx and DMAC_DSCRx registers at
the end of a buffer transfer match described in Row 1 of
DMAC then knows that the previous buffer transferred was the last buffer in the DMAC
transfer. The DMAC transfer might look like that shown in
The LLI.DMAC_SADDRx, LLI. DMAC_DADDRx, LLI.DMAC_DSCRx, LLI.DMAC_CTRLAx and
LLI.DMAC_CTRLBx registers are fetched. The DMAC automatically reprograms the
DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLBx and DMAC_CTRLAx chan-
nel registers from the DMAC_DSCRx(0).
Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the
LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the poll LLI.DMAC_CTRLAx.DONE bit is
asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLAx.DONE bit was cleared
at the start of the transfer.
Table
31-3.
483.
Figure 31-5 on page 482
shows a Linked List example with two
Table 31-3 on page
Figure 31-6 on page
SAM9G35
SAM9G35
483. The
488.
487
487