SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 206

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

22.13.11 PMC Master Clock Register
Name:
Access:
• CSS: Master/Processor Clock Source Selection
• PRES: Master/Processor Clock Prescaler
• MDIV: Master Clock Division
206
31
23
15
–
–
–
7
–
Value
Value
Value
0
1
2
3
SAM9G35
0
1
2
3
0
1
2
3
4
5
6
7
30
22
14
Name
EQ_PCK
PCK_DIV2
PCK_DIV4
PCK_DIV3
PMC_MCKR
Read-write
–
–
–
6
Name
SLOW_CLK
MAIN_CLK
PLLA_CLK
UPLL_CLK
Name
CLOCK
CLOCK_DIV2
CLOCK_DIV4
CLOCK_DIV8
CLOCK_DIV16
CLOCK_DIV32
CLOCK_DIV64
CLOCK_DIV3
PRES
29
21
13
–
–
–
5
PLLADIV2
Description
Master Clock is Prescaler Output Clock divided by 1.
Warning: DDRCK is not available.
Master Clock is Prescaler Output Clock divided by 2.
DDRCK is equal to MCK.
Master Clock is Prescaler Output Clock divided by 4.
DDRCK is equal to MCK.
Master Clock is Prescaler Output Clock divided by 3.
DDRCK is equal to MCK.
28
20
12
–
–
4
Description
Selected clock
Selected clock divided by 2
Selected clock divided by 4
Selected clock divided by 8
Selected clock divided by 16
Selected clock divided by 32
Selected clock divided by 64
Selected clock divided by 3
Description
Slow Clock is selected
Main Clock is selected
PLLACK/PLLADIV2 is selected
UPLL Clock is selected
27
19
11
–
–
–
–
3
26
18
10
–
–
–
2
–
25
17
–
–
9
1
11053B–ATARM–22-Sep-11
MDIV
CSS
24
16
–
–
8
0