SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 443

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

30.5.4
30.5.4.1
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Power Management
Self Refresh Mode
This mode is activated by setting low-power command bits [LPCB] to ‘01’ in the
DDRSDRC_LPR Register
Self refresh mode is used to reduce power consumption, i.e., when no access to the SDRAM
device is possible. In this case, power consumption is very low. In self refresh mode, the
SDRAM device retains data without external clocking and provides its own internal clocking,
thus performing its own auto-refresh cycles. All the inputs to the SDRAM device become “don’t
care” except CKE, which remains low. As soon as the SDRAM device is selected, the DDRS-
DRC provides a sequence of commands and exits self refresh mode.
The DDRSDRC re-enables self refresh mode as soon as the SDRAM device is not selected. It is
possible to define when self refresh mode will be enabled by setting the register LPR (see
tion 30.7.7 “DDRSDRC Low-power Register” on page
As soon as the SDRAM device is no longer selected, PRECHARGE ALL BANKS command is
generated followed by a SELF-REFREFSH command. If, between these two commands an
SDRAM access is detected, SELF-REFREFSH command will be replaced by an AUTO-
REFRESH command. According to the application, more AUTO-REFRESH commands will be
performed when the self refresh mode is enabled during the application.
This controller also interfaces low-power SDRAM. These devices add a new feature: A single
quarter, one half quarter or all banks of the SDRAM array can be enabled in self refresh mode.
Disabled banks will be not refreshed in self refresh mode. This feature permits to reduce the self
refresh current. The extended mode register controls this feature, it includes Temperature Com-
pensated Self Refresh (TSCR), Partial Array Self Refresh (PASR) parameters and Drive
Strength (DS). These parameters are set during the initialization phase. After initialization, as
soon as PASR/DS/TCSR fields are modified, the Extended Mode Register in the memory of the
external device is accessed automatically and PASR/DS/TCSR bits are updated before entry
into self refresh mode if DDRSDRC does not share an external bus with another controller or
during a refresh command, and a pending read or write access, if DDRSDRC does share an
external bus with another controller. This type of update is a function of the UPD_MR bit (see
Section 30.7.7 “DDRSDRC Low-power Register” on page
The low-power SDR-SDRAM must remain in self refresh mode for a minimum period of TRAS
periods and may remain in self refresh mode for an indefinite period. (See
The low-power DDR1-SDRAM must remain in self refresh mode for a minimum of TRFC periods
and may remain in self refresh mode for an indefinite period.
The DDR2-SDRAM must remain in self refresh mode for a minimum of TCKE periods and may
remain in self refresh mode for an indefinite period.
• 00 = Self refresh mode is enabled as soon as the SDRAM device is not selected
• 01 = Self refresh mode is enabled 64 clock cycles after completion of the last access
• 10 = Self refresh mode is enabled 128 clock cycles after completion of the last access
465), timeout command bit:
465).
Figure
SAM9G35
SAM9G35
30-17)
Sec-
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