SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 301

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

25.5.3.3
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Drive Level and Delay Control
and pull-down resistors on the D0 - D15 lines. Pull-up or pull-down resistors on the D16 - D31
lines can be performed by programming the appropriate PIO controller.
The EBI I/Os accept two drive levels, HIGH and LOW. This allows to avoid overshoots and give
the best performance according to the bus load and external memories.
The slew rates are determined by programming EBI_DRIVE field in the Chip Configuration regis-
ters located in the Matrix User Interface.
At reset the selected current drive is LOW.
To improve EMI, programmable delay has been inserted on lines able to run at high speed. The
control of these delays is as follows:
D[15:0] controlled by 2 registers DELAY1 and DELAY2 located in the SMC user interface.
D[31:16] on PIOD[21:6] controlled by 2 registers, DELAY3 and DELAY4 located in the SMC
user interface.
Note:
A[25:0], controlled by 4 registers DELAY5, DELAY6, DELAY7 and DELAY8 located in the SMC
user interface.
• EBI (DDR2SDRC\SMC\NAND Flash)
– D[0] <=> DELAY1[3:0],
– D[1] <=> DELAY1[7:4],...,
– D[6] <=> DELAY1[27:24],
– D[7] <=> DELAY1[31:28]
– D[8] <=> DELAY2[3:0],
– D[9] <=> DELAY2[7:4],...,
– D[14] <=> DELAY2[27:24],
– D[15] <=> DELAY2[31:28]
– D[16] <=> DELAY3[3:0],
– D[17] <=> DELAY3[7:4],...,
– ...
– D[24] <=> DELAY4[3:0]
– D[25] <=> DELAY4[7:4]
– D[26] <=> DELAY4[11:8]
– D[27] <=> DELAY4[15:12]
– D[28] <=> DELAY4[19:16]
– D[29] <=> DELAY4[23:20]
– D[30] <=> DELAY4[27:24]
– D[31] <=> DELAY4[31:28]
– A[0] <=> DELAY5[3:0]
– A[1] <=> DELAY5[7:4],...,
– ...
1. A20, A23, A24 and A25 are multiplexed with D25, D26, D27 and D28 in PIOD, on PD15, PD16,
PD17 and PD18 lines respectively. Delays applied on these IO lines are common to A20, A23,
A24, A25 and D25, D26, D27, D28 respectively.
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SAM9G35
SAM9G35
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