SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 588

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

33.7.14
Name:
Address:
Access:
• EPT_ENABL: Endpoint Enable
0 = If cleared, the endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a
hardware or UDPHS bus reset and participate in the device configuration.
1 = If set, the endpoint is enabled according to the device configuration.
• AUTO_VALID: Packet Auto-Valid Enabled (Not for CONTROL Endpoints)
Set this bit to automatically validate the current packet and switch to the next bank for both IN and OUT endpoints.
• INTDIS_DMA: Interrupt Disables DMA
If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled regardless of the
UDPHS_IEN register EPT_x bit for this endpoint. Then, the firmware will have to clear or disable the interrupt source or
clear this bit if transfer completion is needed.
588
588
SHRT_PCKT
MDATA_RX
NAK_OUT
For IN Transfer:
If this bit is set, then the UDPHS_EPTSTAx register TX_PK_RDY bit is set automatically when the current bank is full
and at the end of DMA buffer if the UDPHS_DMACONTROLx register END_B_EN bit is set.
The user may still set the UDPHS_EPTSTAx register TX_PK_RDY bit if the current bank is not full, unless the user
wants to send a Zero Length Packet by software.
For OUT Transfer:
If this bit is set, then the UDPHS_EPTSTAx register RX_BK_RDY bit is automatically reset for the current bank when
the last packet byte has been read from the bank FIFO or at the end of DMA buffer if the UDPHS_DMACONTROLx
register END_B_EN bit is set. For example, to truncate a padded data packet when the actual data transfer size is
reached.
The user may still clear the UDPHS_EPTSTAx register RX_BK_RDY bit, for example, after completing a DMA buffer
by software if UDPHS_DMACONTROLx register END_B_EN bit was disabled or in order to cancel the read of the
remaining data bank(s).
31
23
15
–
7
SAM9G35
SAM9G35
UDPHS Endpoint Control Register
UDPHS_EPTCTLx [x=0..6]
0xF803C10C [0], 0xF803C12C [1], 0xF803C14C [2], 0xF803C16C [3], 0xF803C18C [4], 0xF803C1AC [5],
0xF803C1CC [6]
Read-only
ERR_FLUSH
DATAX_RX
NAK_IN/
30
22
14
–
–
6
ERR_CRISO/
ERR_NBTRA
STALL_SNT/
29
21
13
–
–
5
–
ERR_FL_ISO
RX_SETUP/
NYET_DIS
28
20
12
–
–
4
TX_PK_RDY/
ERR_TRANS
INTDIS_DMA
27
19
11
–
–
3
BUSY_BANK
TX_COMPLT
26
18
10
–
2
–
AUTO_VALID
RX_BK_RDY
25
17
–
–
9
1
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
ERR_OVFLW
EPT_ENABL
24
16
–
–
8
0