SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 856

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 39-52. Master Node with DMAC (PDCM = 0)
Figure 39-53. Slave Node with DMAC
39.7.8.17
856
856
WRITE BUFFER
Slave Node Configuration
WRITE BUFFER
DATA 0
DATA N
IDENTIFIER
DATA 0
DATA N
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SAM9G35
SAM9G35
Wake-up Request
(Peripheral) DMA
Controller
In this configuration, the DMAC transfers only the DATA. The Identifier must be read by the user
in the LIN Identifier register (US_LINIR). The LIN mode must be written by the user in the LIN
Mode register (US_LINMR).
The WRITE buffer contains the DATA if the USART sends the response (NACT=PUBLISH).
T h e R E A D b u f f e r c o n t a i n s t h e D A T A i f t h e U S A R T r e c e i v e s t h e r e s p o n s e
(NACT=SUBSCRIBE).
Any node in a sleeping LIN cluster may request a wake-up.
In the LIN 2.0 specification, the wakeup request is issued by forcing the bus to the dominant
state from 250 μs to 5 ms. For this, it is necessary to send the character 0xF0 in order to impose
5 successive dominant bits. Whatever the baud rate is, this character respects the specified
timings.
In the LIN 1.3 specification, the wakeup request should be generated with the character 0x80 in
order to impose 8 successive dominant bits.
• Baud rate min = 1 kbit/s -> Tbit = 1ms -> 5 Tbits = 5 ms
• Baud rate max = 20 kbit/s -> Tbi t= 50 μs -> 5 Tbits = 250 μs
(DMA)
PDC
APB bus
TXRDY
APB bus
TXRDY
LIN CONTROLLER
NODE ACTION = PUBLISH
USART3
LIN CONTROLLER
USART3
READ BUFFER
DATA N
WRITE BUFFER
DATA 0
READ BUFFER
IDENTIFIER
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DATA N
DATA 0
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(Peripheral) DMA
(DMA)
PDC
Controller
APB bus
TXRDY
RXRDY
APB bus
RXRDY
NODE ACTION = SUBSCRIBE
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
LIN CONTROLLER
NACT = SUBSCRIBE
USART3
LIN CONTROLLER
USART3