SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 675

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 35-7.
35.7.3.3
35.7.3.4
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
(from master)
(from slave)
TXEMPTY
NPCS0
SPCK
TDRE
MOSI
RDRF
MISO
SPI_TDR
Clock Generation
Transfer Delays
Write in
Status Register Flags Behavior
Figure 35-7
Transmission Register Empty (TXEMPTY) status flags behavior within the SPI_SR (Status Reg-
ister) during an 8-bit data transfer in fixed mode and no Peripheral Data Controller involved.
The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1
and 255.
This allows a maximum operating baud rate at up to Master Clock and a minimum operating
baud rate of MCK divided by 255.
Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead
to unpredictable results.
At reset, SCBR is 0 and the user has to program it at a valid value before performing the first
transfer.
The divisor can be defined independently for each chip select, as it has to be programmed in the
SCBR field of the Chip Select Registers. This allows the SPI to automatically adapt the baud
rate for each interfaced peripheral without reprogramming.
Figure 35-8
select. Three delays can be programmed to modify the transfer waveforms:
MSB
• The delay between chip selects, programmable only once for all the chip selects by writing
1
MSB
the DLYBCS field in the Mode Register. Allows insertion of a delay between release of one
chip select and before assertion of a new one.
shows Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and
2
shows a chip select transfer change and consecutive transfers on the same chip
6
6
3
5
5
4
4
4
5
3
3
6
6
2
2
7
1
1
shift register empty
8
LSB
LSB
SAM9G35
SAM9G35
RDR read
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