SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 542

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

33.6.4
33.6.5
542
542
SAM9G35
SAM9G35
USB V2.0 High Speed BUS Transactions
Endpoint Configuration
Each transfer results in one or more transactions over the USB bus.
There are five kinds of transactions flowing across the bus in packets:
Figure 33-4. Control Read and Write Sequences
A status IN or OUT transaction is identical to a data IN or OUT transaction.
The endpoint 0 is always a control endpoint, it must be programmed and active in order to be
enabled when the End Of Reset interrupt occurs.
To configure the endpoints:
Note: For control endpoints the direction has no effect.
Control endpoints can generate interrupts and use only 1 bank.
1. Setup Transaction
2. Data IN Transaction
3. Data OUT Transaction
4. Status IN Transaction
5. Status OUT Transaction
• Fill the configuration register (UDPHS_EPTCFG) with the endpoint size, direction (IN or
• Fill the number of transactions (NB_TRANS) for isochronous endpoints.
• Verify that the EPT_MAPD flag is set. This flag is set if the endpoint size and the number of
• Configure control flags of the endpoint and enable it in UDPHS_EPTCTLENBx according to
OUT), type (CTRL, Bulk, IT, ISO) and the number of banks.
banks are correct compared to the FIFO maximum capacity and the maximum number of
allowed banks.
“UDPHS Endpoint Control Register” on page
Control Write
Control Read
No Data
Control
Setup Stage
Setup Stage
Setup Stage
Setup TX
Setup TX
Setup TX
Status Stage
Status IN TX
Data OUT TX
Data IN TX
Data Stage
Data Stage
588.
Data OUT TX
Data IN TX
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Status OUT TX
Status Stage
Status Stage
Status IN TX