SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 321

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

26.5.2
26.5.2.1
26.5.2.2
11053B–ATARM–22-Sep-11
Arbitration Priority Scheme
Round-Robin Arbitration
Fixed Priority Arbitration
Warning: This feature cannot prevent any slave from locking its access indefinitely.
The bus Matrix arbitration scheme is organized in priority pools.
Round-robin priority is used in the highest and lowest priority pools, whereas fixed level priority
is used between priority pools and in the intermediate priority pools.
For each slave, each master is assigned to one of the slave priority pools through the priority
registers for slaves (MxPR fields of MATRIX_PRAS and MATRIX_PRBS). When evaluating
master requests, this programmed priority level always takes precedence.
After reset, all the masters belong to the lowest priority pool (MxPR = 0) and are therefore
granted bus access in a true round-robin order.
The highest priority pool must be specifically reserved for masters requiring very low access
latency. If more than one master belongs to this pool, they will be granted bus access in a biased
round-robin manner which allows tight and deterministic maximum access latency from AHB bus
requests. At worst, any currently occurring high-priority master request will be granted after the
current bus master access has ended and other high priority pool master requests, if any, have
been granted once each.
The lowest priority pool shares the remaining bus bandwidth between AHB Masters.
Intermediate priority pools allow fine priority tuning. Typically, a moderately latency-critical mas-
ter or a bandwidth-only critical master will use such a priority level. The higher the priority level
(MxPR value), the higher the master priority.
All combinations of MxPR values are allowed for all masters and slaves. For example some
masters might be assigned to the highest priority pool (round-robin) and the remaining masters
to the lowest priority pool (round-robin), with no master for intermediate fix priority levels.
If more than one master requests the slave bus, irregardless of the respective masters priorities,
no master will be granted the slave bus for two consecutive runs. A master can only get back-to-
back grants so long as it is the only requesting master.
Fixed priority arbitration algorithm is the first and only arbitration algorithm applied between mas-
ters from distinct priority pools. It is also used in priority pools other than the highest and lowest
priority pools (intermediate priority pools).
Fixed priority arbitration allows the Bus Matrix arbiters to dispatch the requests from different
masters to the same slave by using the fixed priority defined by the user in the MxPR field for
each master in the Priority Registers, MATRIX_PRAS and MATRIX_PRBS. If two or more mas-
ter requests are active at the same time, the master with the highest priority MxPR number is
serviced first.
In intermediate priority pools, if two or more master requests with the same priority are active at
the same time, the master with the highest number is serviced first.
This algorithm is only used in the highest and lowest priority pools. It allows the Bus Matrix arbi-
ters to properly dispatch requests from different masters to the same slave. If two or more
master requests are active at the same time in the priority pool, they are serviced in a
round-robin increasing master number order.
SAM9G35
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