SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 548

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

33.6.9
33.6.9.1
33.6.9.2
548
548
SAM9G35
SAM9G35
Handling Transactions with USB V2.0 Device Peripheral
Setup Transaction
NYET
The setup packet is valid in the DPR while RX_SETUP is set. Once RX_SETUP is cleared by
the application, the UDPHS accepts the next packets sent over the device endpoint.
When a valid setup packet is accepted by the UDPHS:
An endpoint interrupt is generated while RX_SETUP in the UDPHS_EPTSTAx register is not
cleared. This interrupt is carried out to the microcontroller if interrupts are enabled for this
endpoint.
Thus, firmware must detect RX_SETUP polling UDPHS_EPTSTAx or catching an interrupt, read
the setup packet in the FIFO, then clear the RX_SETUP bit in the UDPHS_EPTCLRSTA register
to acknowledge the setup stage.
If STALL_SNT was set to 1, then this bit is automatically reset when a setup token is detected by
the device. Then, the device still accepts the setup stage. (See
page
NYET is a High Speed only handshake. It is returned by a High Speed endpoint as part of the
PING protocol.
High Speed devices must support an improved NAK mechanism for Bulk OUT and control end-
points (except setup stage). This mechanism allows the device to tell the host whether it has
sufficient endpoint space for the next OUT transfer (see USB 2.0 spec 8.5.1 NAK Limiting via
Ping Flow Control).
The NYET/ACK response to a High Speed Bulk OUT transfer and the PING response are auto-
matically handled by hardware in the UDPHS_EPTCTLx register (except when the user wants to
force a NAK response by using the NYET_DIS bit).
If the endpoint responds instead to the OUT/DATA transaction with an NYET handshake, this
means that the endpoint accepted the data but does not have room for another data payload.
The host controller must return to using a PING token until the endpoint indicates it has space
available.
• the UDPHS device automatically acknowledges the setup packet (sends an ACK response)
• payload data is written in the endpoint
• sets the RX_SETUP interrupt
• the BYTE_COUNT field in the UDPHS_EPTSTAx register is updated
command
// Clear DMA channel status (read the register for clear it)
AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMASTATUS;
}
559).
AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMACONTROL = 0;
AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMASTATUS =
Section 33.6.9.15 “STALL” on
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
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