SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 929

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

Figure 41-13. Buffer Structure when only touchscreen channels are enabled
41.7.10.3
11053B–ATARM–22-Sep-11
trig.event1
trig.event2
trig.eventN
trig.eventN
trig.event1
trig.event2
Assuming ADC_TSMR(TSMOD) = 1 or 3
ADC_TSMR(TSAV) = 0
ADC_CHSR = 0x000_00000 , ADC_EMR(TAG) = 1
Assuming ADC_TSMR(TSMOD) = 2
ADC_TSMR(TSAV) = 0
ADC_CHSR = 0x000_00000 , ADC_EMR(TAG) = 1
DMA Buffer
Structure
DMA Buffer
Structure
Interleaved Channels
0
1
0
1
0
1
0
1
2
3
0
1
2
3
0
1
2
3
When both classic ADC channels (CH4/CH5 up to CH12 are set in ADC_CHSR) and touch-
screen conversions are required (TSMODE differs from 0 in ADC_TSMR register) the structure
of the buffer differs according to TSAV and TSFREQ values.
If TSFREQ differs from 0, not all events generate touchscreen conversions, therefore buffer
structure is based on 2
screen conversion results depends on TSAV value.
ADC_XPOSR
ADC_YPOSR
ADC_XPOSR
ADC_YPOSR
ADC_XPOSR
ADC_YPOSR
ADC_XPOSR
ADC_YPOSR
ADC_PRESSR(Z1)
ADC_PRESSR(Z2)
ADC_XPOSR
ADC_YPOSR
ADC_PRESSR(Z1)
ADC_PRESSR(Z2)
ADC_XPOSR
ADC_YPOSR
ADC_PRESSR(Z1)
ADC_PRESSR(Z2)
TSFREQ
Base Address (BA)
BA + 0x02
BA + 0x04
BA + 0x06
BA + [(N-1) * 4]
BA + [(N-1) * 4]+ 0x02
DMA Transfer
Base Address (BA)
BA + 0x02
BA + 0x04
BA + 0x06
BA + 0x08
BA + 0x0A
BA + 0x0C
BA + 0x0E
BA + [(N-1) * 8]
BA + [(N-1) * 8]+ 0x02
BA + [(N-1) * 8]+ 0x04
BA + [(N-1) * 8]+ 0x06
DMA Transfer
trigger events. Given a TSFREQ value, the location of touch-
trig.eventN
trig.event1
trig.event2
trig.event1
trig.event2
trig.eventN
Assuming ADC_TSMR(TSMOD) =1 or 3
ADC_TSMR(TSAV) = 0
ADC_CHSR = 0x000_00000 , ADC_EMR(TAG) = 0
Assuming ADC_TSMR(TSMOD) = 2
ADC_TSMR(TSAV) = 0
ADC_CHSR = 0x000_00000 , ADC_EMR(TAG) = 0
DMA Buffer
Structure
DMA Buffer
Structure
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADC_XPOSR
ADC_YPOSR
ADC_XPOSR
ADC_YPOSR
ADC_XPOSR
ADC_YPOSR
ADC_XPOSR
ADC_YPOSR
ADC_PRESSR(Z1)
ADC_PRESSR(Z2)
ADC_XPOSR
ADC_YPOSR
ADC_PRESSR(Z1)
ADC_PRESSR(Z2)
ADC_XPOSR
ADC_YPOSR
ADC_PRESSR(Z1)
ADC_PRESSR(Z2)
SAM9G35
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