SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 614

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

34.8.1
614
614
SAM9G35
SAM9G35
Command - Response Operation
Both read and write operations allow either single or multiple block transmission. A multiple
block transmission is terminated when a stop command follows on the CMD line similarly to the
sequential read or when a multiple block transmission has a pre-defined block count
Transfer Operation” on page
The HSMCI provides a set of registers to perform the entire range of High Speed MultiMedia
Card operations.
After reset, the HSMCI is disabled and becomes valid after setting the MCIEN bit in the
HSMCI_CR Control Register.
The PWSEN bit saves power by dividing the HSMCI clock by 2
inactive.
The two bits, RDPROOF and WRPROOF in the HSMCI Mode Register (HSMCI_MR) allow
stopping the HSMCI Clock during read or write access if the internal FIFO is full. This will guar-
antee data integrity, not bandwidth.
All the timings for High Speed MultiMedia Card are defined in the High Speed MultiMediaCard
System Specification.
The two bus modes (open drain and push/pull) needed to process all the operations are defined
in the HSMCI command register. The HSMCI_CMDR allows a command to be carried out.
For example, to perform an ALL_SEND_CID command:
The command ALL_SEND_CID and the fields and values for the HSMCI_CMDR Control Regis-
ter are described in
Table 34-6.
Note:
Table 34-7.
CMD
CMD Index
CMD2
Field
CMDNB (command number)
RSPTYP (response type)
SPCMD (special command)
OPCMD (open drain command)
MAXLAT (max latency for command to response)
• Block-oriented commands: These commands send a data block succeeded by CRC bits.
bcr means broadcast command with response.
S
T
ALL_SEND_CID Command Description
Fields and Values for HSMCI_CMDR Command Register
Type
bcr
Host Command
Content
Table 34-6
Argument
[31:0] stuff bits
CRC
617.).
and
Table
E
Z
34-7.
N
Resp
R2
ID
******
Cycles
Value
2 (CMD2)
2 (R2: 136 bits response)
0 (not a special command)
1
0 (NID cycles ==> 5 cycles)
Abbreviation
ALL_SEND_CID
Z
S
T
Content
PWSDIV
CID
Command
Description
Asks all cards to send
their CID numbers on
the CMD line
+ 1 when the bus is
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Z
(See “Data
Z
Z