SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 29

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

9. ARM926EJ-S
9.1
9.2
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Description
Embedded Characteristics
™
The ARM926EJ-S processor is a member of the ARM9
sors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multi-
tasking applications where full memory management, high performance, low die size and low
power are all important features.
The ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets,
enabling the user to trade off between high performance and high code density. It also supports
8-bit Java instruction set and includes features for efficient execution of Java bytecode, provid-
ing a Java performance similar to a JIT (Just-In-Time compilers), for the next generation of Java-
powered wireless and embedded devices. It includes an enhanced multiplier design for
improved DSP performance.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist
in both hardware and software debug.
The ARM926EJ-S provides a complete high performance processor subsystem, including:
• an ARM9EJ-S
• a Memory Management Unit (MMU)
• separate instruction and data AMBA AHB bus interfaces
• ARM9EJ-S
• Three Instruction Sets
• 5-Stage Pipeline Architecture when Jazelle is not Used
• 6-Stage Pipeline when Jazelle is Used
• ICache and DCache
– ARM
– Thumb
– Jazelle
– Fetch (F)
– Decode (D)
– Execute (E)
– Memory (M)
– Writeback (W)
– Fetch
– Jazelle/Decode (Two Cycles)
– Execute
– Memory
– Writeback
– Virtually-addressed 4-way Set Associative Caches
– 8 Words per Line
– Critical-word First Cache Refilling
®
™
High-performance 32-bit Instruction Set
®
®
High Code Density 16-bit Instruction Set
8-bit Instruction Set
Based on ARM
™
integer core
®
Architecture v5TEJ with Jazelle Technology
™
family of general-purpose microproces-
SAM9G35
SAM9G35
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