SAM9G10 Atmel Corporation, SAM9G10 Datasheet - Page 736

• Manufacturer Part Number: SAM9G10
• Manufacturer: Atmel Corporation

Specifications of SAM9G10

• Flash (kbytes): 0 Kbytes
• Pin Count: 217
• Max. Operating Frequency: 266 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 96
• Ext Interrupts: 96
• Usb Transceiver: 3
• Usb Speed: Full Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 1
• Uart: 4
• Ssc: 3
• Sd / Emmc: 1
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: No
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 16
• Self Program Memory: NO
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 1.08 to 1.32
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 3
• Output Compare Channels: 3
• Input Capture Channels: 3
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

42.2.11.5
42.2.11.6
42.2.12
42.2.12.1
42.2.13
42.2.13.1
738
SAM9G10
UDP
UHP
SSC: Data Sent Without Any Frame Synchro
SSC: Unexpected Delay on TD Output
UDP: Bad Data in the First IN Data Stage
UHP: Non-ISO IN transfers
When SSC is configured with the following conditions:
The data is send but there isn’t any toggle of the TF line.
Transmit STTDLY must be different from 0.
When SSC is configured with the following conditions:
An unexpected delay of 2 or 3 system clock cycles is added to TD output.
None.
All or part of the data of the first IN data Stage are not transmitted. It may then be a Zero Length
Packet. The CRC is correct. So the HOST may only see that the size of the received data does
not match the requested length. But even if performed again, the control transfer will probably
fail.
These Control transfers are mainly used at device configuration. After clearing RXSETUP, the
software needs to compute the setup transaction request before writing data into the FIFO if
needed. This time is generally greater than the minimum safe delay required above. If not, a
software wait loop after RXSETUP clear may be added at minimum cost.
Conditions:
Consider the following sequence:
• RF is in input,
• TD is synchronized on a receive START (any condition: START field = 2 to 7)
• TF toggles at each start of data transfer,
• Transmit STTDLY = 0
• Check TD and TF after a receive START,
• TCMR.STTDLY more than 0
• RCMR.START = Start on falling edge / Start on Rising edge / Start on any edge
• RFMR.FSOS = None (input)
• TCMR.START = Receive Start
1. The Host controller issues an IN token.
2. The Device provides the IN data in a short packet.
3. The Host controller writes the received data to the system memory.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
6462B–ATARM–6-Sep-11