SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 1012
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SAM9G45
Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G45.pdf
(10 pages)
5.SAM9G45.pdf
(55 pages)
6.SAM9G45.pdf
(1196 pages)
Specifications of SAM9G45
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G45 PDF datasheet #4
- SAM9G45 PDF datasheet #5
- SAM9G45 PDF datasheet #6
- Current page: 1012 of 1274
- Download datasheet (30Mb)
44.4.2.3
1012
1012
SAM9G35
SAM9G35
Transmit Buffer
best to write the pointer register with the least three significant bits set to zero. As receive buffers
are used, the receive buffer manager sets bit zero of the first word of the descriptor to indicate
used. If a receive error is detected the receive buffer currently being written is recovered. Previ-
ous buffers are not recovered. Software should search through the used bits in the buffer
descriptors to find out how many frames have been received. It should be checking the start-of-
frame and end-of-frame bits, and not rely on the value returned by the receive buffer queue
pointer register which changes continuously as more buffers are used.
For CRC errored frames, excessive length frames or length field mismatched frames, all of
which are counted in the statistics registers, it is possible that a frame fragment might be stored
in a sequence of receive buffers. Software can detect this by looking for start of frame bit set in a
buffer following a buffer with no end of frame bit set.
For a properly working Ethernet system, there should be no excessively long frames or frames
greater than 128 bytes with CRC/FCS errors. Collision fragments are less than 128 bytes long.
Therefore, it is a rare occurrence to find a frame fragment in a receive buffer.
If bit zero is set when the receive buffer manager reads the location of the receive buffer, then
the buffer has already been used and cannot be used again until software has processed the
frame and cleared bit zero. In this case, the DMA block sets the buffer not available bit in the
receive status register and triggers an interrupt.
If bit zero is set when the receive buffer manager reads the location of the receive buffer and a
frame is being received, the frame is discarded and the receive resource error statistics register
is incremented.
A receive overrun condition occurs when bus was not granted in time or because HRESP was
not OK (bus error). In a receive overrun condition, the receive overrun interrupt is asserted and
the buffer currently being written is recovered. The next frame received with an address that is
recognized reuses the buffer.
If bit 17 of the network configuration register is set, the FCS of received frames shall not be cop-
ied to memory. The frame length indicated in the receive status field shall be reduced by four
bytes in this case.
Frames to be transmitted are stored in one or more transmit buffers. Transmit buffers can be
between 0 and 2047 bytes long, so it is possible to transmit frames longer than the maximum
length specified in IEEE Standard 802.3. Zero length buffers are allowed. The maximum number
of buffers permitted for each transmit frame is 128.
The start location for each transmit buffer is stored in memory in a list of transmit buffer descrip-
tors at a location pointed to by the transmit buffer queue pointer register. Each list entry consists
of two words, the first being the byte address of the transmit buffer and the second containing
the transmit control and status. Frames can be transmitted with or without automatic CRC gen-
eration. If CRC is automatically generated, pad is also automatically generated to take frames to
a minimum length of 64 bytes.
descriptor list. To transmit frames, the buffer descriptors must be initialized by writing an appro-
priate byte address to bits 31 to 0 in the first word of each list entry. The second transmit buffer
descriptor is initialized with control information that indicates the length of the buffer, whether or
not it is to be transmitted with CRC and whether the buffer is the last buffer in the frame.
After transmission, the control bits are written back to the second word of the first buffer along
with the “used” bit and other status information. Bit 31 is the “used” bit which must be zero when
Table 44-2 on page 1013
defines an entry in the transmit buffer
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
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