SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 699
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SAM9G45
Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G45.pdf
(10 pages)
5.SAM9G45.pdf
(55 pages)
6.SAM9G45.pdf
(1196 pages)
Specifications of SAM9G45
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
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- SAM9261 PDF datasheet #3
- SAM9G45 PDF datasheet #4
- SAM9G45 PDF datasheet #5
- SAM9G45 PDF datasheet #6
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36.4
36.5
36.5.1
36.5.2
36.5.3
36.6
36.6.1
36.6.2
36.6.3
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Pin Name List
Product Dependencies
Functional Description
I/O Lines
Power Management
Interrupt
TC Description
32-bit Counter
Clock Selection
Table 36-3.
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines.
The programmer must first program the PIO controllers to assign the TC pins to their peripheral
functions.
The TC is clocked through the Power Management Controller (PMC), thus the programmer must
first configure the PMC to enable the Timer Counter clock.
The TC has an interrupt line connected to the Interrupt Controller (IC). Handling the TC interrupt
requires programming the IC before configuring the TC.
The three channels of the Timer Counter are independent and identical in operation . The regis-
ters for channel programming are listed in
Each channel is organized around a 32-bit counter. The value of the counter is incremented at
each positive edge of the selected clock. When the counter has reached the value 0xFFFF and
passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set.
The current value of the counter is accessible in real time by reading the Counter Value Regis-
ter, TC_CV. The counter can be reset by a trigger. In this case, the counter value passes to
0x0000 on the next valid edge of the selected clock.
At block level, input clock signals of each channel can either be connected to the external inputs
TCLK0, TCLK1 or TCLK2, or be connected to the internal I/O signals TIOA0, TIOA1 or TIOA2
for chaining by programming the TC_BMR (Block Mode). See
Selection”.
Each channel can independently select an internal or external clock source for its counter:
•
•
Pin Name
TCLK0-TCLK2
TIOA0-TIOA2
TIOB0-TIOB2
Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3,
TIMER_CLOCK4, TIMER_CLOCK5
External clock signals: XC0, XC1 or XC2
TC pin list
External Clock Input
I/O Line A
I/O Line B
Description
Table 36-4 on page
713.
Figure 36-2 ”Clock Chaining
Type
Input
I/O
I/O
SAM9G35
SAM9G35
699
699
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