SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 186
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SAM9G45
Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G45.pdf
(10 pages)
5.SAM9G45.pdf
(55 pages)
6.SAM9G45.pdf
(1196 pages)
Specifications of SAM9G45
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G45 PDF datasheet #4
- SAM9G45 PDF datasheet #5
- SAM9G45 PDF datasheet #6
- Current page: 186 of 1274
- Download datasheet (30Mb)
22.4
22.5
186
Block Diagram
Processor Clock Controller
SAM9G35
Figure 22-2. General Clock Block Diagram
The PMC features a Processor Clock Controller (PCK) that implements the Processor Idle
Mode. The Processor Clock can be disabled by writing the System Clock Disable Register
(PMC_SCDR). The status of this clock (at least for debug purpose) can be read in the System
Clock Status Register (PMC_SCSR).
The Processor Clock PCK is enabled after a reset and is automatically re-enabled by any
enabled interrupt. The Processor Idle Mode is achieved by disabling the Processor Clock and
entering Wait for Interrupt Mode. The Processor Clock is automatically re-enabled by any
enabled fast or normal interrupt, or by reset of the product.
Note: The ARM Wait for Interrupt mode is entered by means of CP15 coprocessor operation.
Refer to the Atmel application note,
Systems, lit. number 6217.
When the Processor Clock is disabled, the current instruction is finished before the clock is
stopped, but this does not prevent data transfers from other masters of the system bus.
PLLACK
/1,/2
UPLLCK
MAINCK
SLCK
USBS
Master Clock Controller
/1,/2,/3,/4,...,/64
Prescaler
MAINCK
UPLLCK
USBDIV+1
SLCK
Optimizing Power Consumption for AT91SAM9261-based
Programmable Clock Controller
/1 /2 /3 /4
X /1 /1.5 /2
/4
Divider
/1,/2,/4,...,/64
Prescaler
UHP12M
UHP48M
ON/OFF
OHCI
USB
USB
EHCI
Clock Controller
Processor
Controller
Peripherals
Clock
ON/OFF
/2
Divider
pck[..]
11053B–ATARM–22-Sep-11
PCK
int
DDRCK
2x MCK
MCK
Periph_clk[..]
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