SAM9G45 Atmel Corporation, SAM9G45 Datasheet - Page 430
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SAM9G45
Manufacturer Part Number
SAM9G45
Description
Manufacturer
Atmel Corporation
Datasheets
1.SAM9261.pdf
(248 pages)
2.SAM9261.pdf
(1274 pages)
3.SAM9261.pdf
(43 pages)
4.SAM9G45.pdf
(10 pages)
5.SAM9G45.pdf
(55 pages)
6.SAM9G45.pdf
(1196 pages)
Specifications of SAM9G45
Flash (kbytes)
0 Kbytes
Pin Count
324
Max. Operating Frequency
400 MHz
Cpu
ARM926
Hardware Qtouch Acquisition
No
Max I/o Pins
160
Ext Interrupts
160
Usb Transceiver
3
Usb Speed
Hi-Speed
Usb Interface
Host, Device
Spi
2
Twi (i2c)
2
Uart
5
Lin
4
Ssc
2
Ethernet
1
Sd / Emmc
2
Graphic Lcd
Yes
Video Decoder
No
Camera Interface
Yes
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
440
Resistive Touch Screen
Yes
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
64
Self Program Memory
NO
External Bus Interface
2
Dram Memory
DDR2/LPDDR, SDRAM/LPSDR
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
0.9 to 1.1
Fpu
No
Mpu / Mmu
No/Yes
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
No
- SAM9261 PDF datasheet
- SAM9261 PDF datasheet #2
- SAM9261 PDF datasheet #3
- SAM9G45 PDF datasheet #4
- SAM9G45 PDF datasheet #5
- SAM9G45 PDF datasheet #6
- Current page: 430 of 1274
- Download datasheet (30Mb)
30.4.3
430
430
SAM9G35
SAM9G35
DDR2-SDRAM Initialization
The initialization sequence is generated by software. The DDR2-SDRAM devices are initialized
by the following sequence:
A minimum pause of 200 μs is provided to precede any signal toggle.
Note:
9. Perform a write access to any low-power DDR1-SDRAM address.
10. Write the refresh rate into the count field in the DDRSDRC Refresh Timer register (see
11. After initialization, the low-power DDR1-SDRAM device is fully functional.
1. Program the memory device type into the Memory Device Register (see
2. Program the features of DDR2-SDRAM device into the Timing Register (asynchronous
3. An NOP command is issued to the DDR2-SDRAM. Program the NOP command into
4. An NOP command is issued to the DDR2-SDRAM. Program the NOP command into
5. An all banks precharge command is issued to the DDR2-SDRAM. Program all banks
6. An Extended Mode Register set (EMRS2) cycle is issued to chose between commer-
7. An Extended Mode Register set (EMRS3) cycle is issued to set the Extended Mode
page
SDRAM to acknowledge this command.
page
SDRAM device requires a refresh every 15.625 μs or 7.81 μs. With a 100 MHz fre-
quency, the refresh timer count register must to be set with (15.625*100 MHz) = 1562
i.e. 0x061A or (7.81*100 MHz) = 781 i.e. 0x030d
on page
timing (trc, tras, etc.)), and into the Configuration Register (number of columns, rows,
banks, cas latency and output drive strength) (see
30.7.4 on page 461
the Mode Register, the application must set Mode to 1 in the Mode Register (see
tion 30.7.1 on page
acknowledge this command. Now clocks which drive DDR2-SDRAM device are
enabled.
the Mode Register, the application must set Mode to 1 in the Mode Register (see
tion 30.7.1 on page
acknowledge this command. Now CKE is driven high.
precharge command into the Mode Register, the application must set Mode to 2 in the
Mode Register (See
SDRAM address to acknowledge this command
cial or high temperature operations. The application must set Mode to 5 in the Mode
Register (see
SDRAM to acknowledge this command. The write address must be chosen so that
BA[1] is set to 1 and BA[0] is set to 0. For example, with a 16-bit 128 MB DDR2-
SDRAM (12 rows, 9 columns, 4 banks) bank address, the DDR2-SDRAM write access
should be done at the address 0x20800000.
Register to “0”. The application must set Mode to 5 in the Mode Register (see
30.7.1 on page
this command. The write address must be chosen so that BA[1] is set to 1 and BA[0] is
set to 1. For example, with a 16-bit 128 MB DDR2-SDRAM (12 rows, 9 columns, 4
banks) bank address, the DDR2-SDRAM write access should be done at the address
0x20C00000.
This address is for example purposes only. The real address is dependent on implementation in
the product.
456) and performing a write access at any location in the low-power DDR1-
457). (Refresh rate = delay between refresh cycles). The low-power DDR1-
467).
Section 30.7.1 on page
456) and perform a write access to the DDR2-SDRAM to acknowledge
456). Perform a write access to any DDR2-SDRAM address to
456). Perform a write access to any DDR2-SDRAM address to
and
Section 30.7.1 on page
Section 30.7.5 on page
456) and perform a write access to the DDR2-
456). Perform a write access to any DDR2-
463).
Section 30.7.3 on page
11053B–ATARM–22-Sep-11
11053B–ATARM–22-Sep-11
Section 30.7.8
458,
Section
Section
Sec-
Sec-
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