SAM9G46 Atmel Corporation, SAM9G46 Datasheet
SAM9G46
Specifications of SAM9G46
Related parts for SAM9G46
SAM9G46 Summary of contents
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... Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os with Schmitt trigger input • Package – 324-ball TFBGA, pitch 0.8 mm AT91SAM ARM-based Embedded MPU SAM9G46 Summary NOTE: This is a summary document. The complete document is available under NDA. For more information, please contact your local Atmel sales office. 11028CS–ATARM–20-Apr-11 ...
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... LCD Controller, resistive touch- screen, camera interface, audio, Ethernet 10/100 and high speed USB and SDIO. With the pro- cessor running at 400MHz and multiple 100+ Mbps data rate peripherals, the SAM9G46 has the performance and bandwidth to the network or local storage media to provide an adequate user experience ...
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... Block Diagram Figure 2-1. SAM9G46 Block Diagram 11028CS–ATARM–20-Apr-11 SAM9G46 PIO 3 ...
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... XOUT Main Oscillator Output XIN32 Slow Clock Oscillator Input XOUT32 Slow Clock Oscillator Output VBG Bias Voltage Reference for USB PCK0 - PCK1 Programmable Clock Output SAM9G46 4 gives details on the signal names classified by peripheral. Active Type Level Power Supplies Power Power Power ...
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... Input Debug Unit - DBGU Input Output Advanced Interrupt Controller - AIC Input Input PIO Controller - PIOA- PIOB - PIOC - PIOD - PIOE I/O I/O SAM9G46 Reference Voltage Comments Driven at 0V only. 0: The device is in backup mode VDDBU 1: The device is running (not in backup mode). Accept between 0V and VDDBU VDDBU ...
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... NRD Read Signal NWE Write Enable NBS0 - NBS3 Byte Mask Signal CFCE1 - CFCE2 CompactFlash Chip Enable CFOE CompactFlash Output Enable CFWE CompactFlash Write Enable CFIOR CompactFlash IO Read SAM9G46 6 Active Type Level I/O I/O I/O DDR Memory Interface- DDR2/LPDDR Controller I/O Output Output Output High Output ...
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... Output Low Output Output Output High Speed Multimedia Card Interface - HSMCIx I/O I/O I/O I/O Output Input Output Input Synchronous Serial Controller - SSCx Output Input I/O I/O I/O I/O SAM9G46 Reference Voltage Comments VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 (1) (1) ...
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... USB Host Port B High Speed Data - DFSDM USB Device Full Speed Data - DFSDP USB Device Full Speed Data + DHSDM USB Device High Speed Data - DHSDP USB Device High Speed Data + SAM9G46 8 Active Type Level AC97 Controller - AC97C Input Output Output Input ...
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... LCD Controller - LCDC Output Output Output Output Output Output Output Output Touch Screen Analog-to-Digital Converter Analog Analog Analog SAM9G46 Reference Voltage Comments (1) MII only, REFCK in RMII (1) MII only (1) (1) ETX0-ETX1 only in RMII (1) MII only (1) RXDV in MII, CRSDV in RMII ...
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... I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Inter- face signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column “Reset State” of the peripheral multiplexing tables. SAM9G46 10 Active Reference ...
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... Package and Pinout The SAM9G46 is delivered in a 324-ball TFBGA package. 4.1 Mechanical Overview of the 324-ball TFBGA Package Figure 4-1 Figure 4-1. 11028CS–ATARM–20-Apr-11 shows the orientation of the 324-ball TFBGA Package Orientation of the 324-ball TFBGA Package ...
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... TFBGA Package Pinout Table 4-1. SAM9G46 Pinout for 324-ball BGA Package Pin Signal Name Pin A1 PC27 E10 A2 PC28 E11 A3 PC25 E12 A4 PC20 E13 A5 PC12 E14 A6 PC7 E15 A7 PC5 E16 A8 PC0 E17 A9 NWR3/NBS3 E18 A10 NCS0 F1 A11 DQS0 F2 A12 RAS F3 A13 SDCK ...
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... Table 4-1. SAM9G46 Pinout for 324-ball BGA Package (Continued) Pin Signal Name Pin C13 D10 H4 C14 D6 H5 C15 D2 H6 C16 GNDIOM H7 C17 A18 H8 C18 A12 H9 D1 XOUT32 H10 D2 PD20 H11 D3 GNDBU H12 D4 VDDBU H13 D5 PC24 H14 D6 PC18 H15 D7 PC13 H16 D8 PC6 H17 ...
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... Power Considerations 5.1 Power Supplies The SAM9G46 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 0.9V to 1.1V, 1.0V typical. • VDDIOM0 pins: Power the DDR2/LPDDR I/O lines; voltage ranges between 1.65V and 1.95V (1.8V typical). • ...
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... Separate Address and Data Buses for both the 32-bit instruction interface and the – On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit • TCM Interface 11028CS–ATARM–20-Apr-11 ® ® technology for Java acceleration each quarter of the page system flexibility 32-bit data interface (Words) SAM9G46 15 ...
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... Allows Handling of Dynamic Exception Vectors 6.2.1 Matrix Masters The Bus Matrix of the SAM9G46 manages Masters, thus each master can perform an access concurrently with others, depending on whether the slave it accesses is available. Each Master has its own decoder, which can be defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings ...
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... The remaining masters share DDR Port 2 and DDR Port 3. 11028CS–ATARM–20-Apr-11 List of Bus Matrix Slaves Internal SRAM Internal ROM USB OHCI USB EHCI UDP High Speed RAM LCD User Interface DDR Port 0 DDR Port 1 DDR Port 2 DDR Port 3 External Bus Interface Internal Peripherals SAM9G46 17 ...
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... Figure 6-1. Table 6-3. SAM9G46 Masters to Slaves Access DDRMP_DIS = 0 Master 0 ARM ARM Slave 926 Instr. 926 Data 0 Internal SRAM 0 X Internal ROM X UHP OHCI X UHP EHCI X LCD User Int. X UDPHS RAM X 1 Reserved X 2 DDR Port DDR Port DDR Port DDR Port 3 ...
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... Table 6-4. SAM9G46 Masters to Slaves Access with DDRMP_DIS = 1 (default) Master 0 ARM Slave 926 Instr. 926 Data 0 Internal SRAM 0 X Internal ROM X UHP OHCI X UHP EHCI X 1 LCD User Int. X UDPHS RAM X Reserved X 2 DDR Port DDR Port DDR Port ...
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... SSC1 SSC0 6.4 USB The SAM9G46 features USB communication ports as follows: • 2 Ports USB Host full speed OHCI and High speed EHCI • 1 Device High speed USB Host Port A is directly connected to the first UTMI transceiver. The Host Port B is multiplexed with the USB device High speed and connected to the second UTMI port ...
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... AES MCI1 11028CS–ATARM–20-Apr-11 USB Selection HS HS Transceiver Transceiver EHCI FS OHCI DMA DMA Channel Definition DMA Channel HW T/R interface Number TX/ TX/RX 13 SAM9G46 EN_UDPHS 1 HS USB DMA 21 ...
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... Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE SAM9G46 22 ® 1149.1 JTAG Boundary-scan on All Digital Pins. 11028CS–ATARM–20-Apr-11 ...
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... Memories Figure 7-1. SAM9G46 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 256M Bytes 0x0FFF FFFF 0x1000 0000 EBI Chip Select 0 256M Bytes 0x1FFF FFFF 0x2000 0000 EBI Chip Select 1/ 256M Bytes DDRSDRC1 0x2FFF FFFF 0x3000 0000 EBI 256M Bytes Chip Select 2 ...
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... Embedded Memories 7.2.1 Internal SRAM The SAM9G46 product embeds a total of 64 Kbytes high-speed SRAM split in 4 blocks of 16 KBytes connected to one slave of the matrix. After reset and until the Remap Command is performed, the four SRAM blocks are contiguous and only accessible at address 0x00300000. ...
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... Note: All the memory blocks can always be seen at their specified base addresses that are not concerned by these parameters. The SAM9G46 Bus Matrix manages a boot memory that depends on the level on the pin BMS at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect ...
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... Program the PMC (main oscillator enable or bypass mode) • Program and Start the PLL • Reprogram the SMC setup, cycle, hold, mode timings registers for EBI CS0 to adapt them to the new clock • Switch the main clock to the new value SAM9G46 26 11028CS–ATARM–20-Apr-11 ...
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... Up to 26-bit Address Bus (up to 64MBytes linear per chip select) • chip selects, Configurable Assignment: – Static Memory Controller on NCS0 – DDR2/SDRAM Controller (SDCS) or Static Memory Controller on NCS1 – Static Memory Controller on NCS2 11028CS–ATARM–20-Apr-11 Average Latency of Transactions) SAM9G46 TM 27 ...
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... NAND Flash Error Corrected Code Controller • Tracking the accesses to a NAND Flash device by triggering on the corresponding chip select • Single bit error correction and 2-bit Random detection. • Automatic Hamming Code Calculation while writing SAM9G46 28 Average Latency of Transactions) M support 11028CS–ATARM–20-Apr-11 ...
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... ECC value available in a register • Automatic Hamming Code Calculation while reading – Error Report, including error flag, correctable error flag and word address being – Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes 11028CS–ATARM–20-Apr-11 detected erroneous pages. SAM9G46 29 ...
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... All the registers of the System Controller can be addressed from a single pointer by using the standard ARM instruction set, as the Load/Store instruction have an indexing mode of ±4 KB. Figure 8-1 on page 31 Figure 7-1 on page 23 peripherals. SAM9G46 30 shows the System Controller block diagram. shows the mapping of the User Interfaces of the System Controller 11028CS–ATARM–20-Apr-11 ...
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... System Controller Block Diagram Figure 8-1. SAM9G46 System Controller Block Diagram periph_irq[2..24] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq periph_nreset periph_nreset proc_nreset NRST VDDCORE POR VDDBU VDDBU POR backup_nreset backup_nreset SHDN WKUP RC OSC SLOW XIN32 CLOCK XOUT32 OSC XIN 12MHz MAIN OSC XOUT ...
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... MHz input, the only limitation being the lowest input frequency shall be higher or equal to 2 MHz. The USB Device and Host HS Clocks are provided by a the dedicated UTMI PLL (UPLL) embedded in the UTMI macro. SAM9G46 32 11028CS–ATARM–20-Apr-11 ...
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... Figure 8-2. 8.6 Slow Clock Selection The SAM9G46 slow clock can be generated either by an external 32768Hz crystal or the on-chip RC oscillator. The 32768 Hz crystal oscillator can be bypassed, by setting the bit OSC32BYP, to accept an external slow clock on XIN32. The internal RC oscillator and the 32768 Hz oscillator can be enabled by setting to 1 respec- tively RCEN bit and OSC32EN bit in the system controller user interface ...
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... Switch the master clock to a source different from slow clock (PLLA or PLLB or Main Oscillator). • Enable the internal RC oscillator by setting the bit RCEN to 1. • Wait internal RC Startup Time for clock stabilization (software loop). SAM9G46 34 Slow Clock Clock Generator On Chip ...
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... Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt • Backup Mode, Main Power Supplies off, VDDBU powered by a battery 11028CS–ATARM–20-Apr-11 DDR system clock is not available when Master Clock (MCK) equals Processor Clock (PCK). SAM9G46 35 ...
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... Full Speed OHCI input clock is UPLLCK, USBDIV is 9 (division by 10) • System Input clock is UPLLCK, Prescaler is 2, PCK is 240 MHz • MDIV is ‘01’, MCK is 120 MHz • Only LP-DDR can be used 120 MHz SAM9G46 36 SAM9G46 Power Management Controller Block Diagram USBS USBDIV+1 UPLLCK X /1 /1.5 /2 Prescaler /1 /2 /1,/2,/4, ...
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... Thirty-two individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.) – Programmable Edge-triggered or Level-sensitive Internal Sources – Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive 11028CS–ATARM–20-Apr-11 Controller SAM9G46 37 ...
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... Debug Communication Channel Support – Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from 8.15 Chip Identification The SAM9G46 Chip ID is defined in the Debug Unit Chip ID Register and Debug Unit Chip ID Extension Register. • Chip ID: 0x819B05A2 • Ext ID: 0x00000003 • ...
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... Multi-drive option enables driving in open drain – Programmable pull up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write 11028CS–ATARM–20-Apr-11 SAM9G46 39 ...
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... UDPHS 28 AES, TDES, SHA SAM9G46 40 Figure 7-1, the Peripherals are mapped in the upper 256 Mbytes of the address defines the Peripheral Identifiers of the SAM9G46. A peripheral identifier is required Peripheral Name Advanced Interrupt Controller System Controller Interrupt Parallel I/O Controller A, Parallel I/O Controller B Parallel I/O Controller C Parallel I/O Controller D, Parallel I/O Controller E ...
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... Peripheral ID. However, there is no clock control associated with these peripheral IDs. 9.4 Peripheral Signals Multiplexing on I/O Lines The SAM9G46 features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which multi- plexes the I/O lines of the peripheral set. Each PIO Controller controls lines. Each line can be assigned to one of two peripheral functions The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two columns “ ...
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... PA20 TWD0 PA21 TWCK0 PA22 MCI1_CDA PA23 MCI1_DA0 PA24 MCI1_DA1 PA25 MCI1_DA2 PA26 MCI1_DA3 PA27 MCI1_DA4 PA28 MCI1_DA5 PA29 MCI1_DA6 PA30 MCI1_DA7 PA31 MCI1_CK SAM9G46 42 Reset Power Peripheral B State Supply TCLK3 I/O VDDIOP0 TIOA3 I/O VDDIOP0 TIOB3 I/O VDDIOP0 TCKL4 I/O VDDIOP0 TIOA4 I/O VDDIOP0 TIOB4 I/O ...
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... VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 ISI_D8 I/O VDDIOP2 ISI_D9 I/O VDDIOP2 ISI_D10 I/O VDDIOP2 ISI_D11 I/O VDDIOP2 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 CTS0 I/O VDDIOP0 SCK0 I/O VDDIOP0 RTS0 I/O VDDIOP0 SPI0_NPCS1 I/O VDDIOP0 SPI0_NPCS2 I/O VDDIOP0 I/O VDDIOP2 I/O VDDIOP2 I/O VDDIOP2 I/O VDDIOP2 I/O VDDIOP2 I/O VDDIOP2 I/O VDDIOP2 I/O VDDIOP2 I/O VDDIOP2 I/O VDDIOP2 I/O VDDIOP2 PCK1 I/O VDDIOP2 SAM9G46 Function Comments 43 ...
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... D21 PC22 D22 PC23 D23 PC24 D24 PC25 D25 PC26 D26 PC27 D27 PC28 D28 PC29 D29 PC30 D30 PC31 D31 SAM9G46 44 Reset Power Peripheral B State Supply DQM2 VDDIOM1 DQM3 VDDIOM1 A19 VDDIOM1 A20 VDDIOM1 A21 VDDIOM1 A22 VDDIOM1 A23 VDDIOM1 ...
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... VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 I/O VDDIOP0 IRQ I/O VDDIOP0 FIQ I/O VDDIOP0 I/O VDDANA I/O VDDANA I/O VDDANA I/O VDDANA PWM0 I/O VDDANA PWM1 I/O VDDANA PWM2 I/O VDDANA SPI0_NPCS3 I/O VDDANA SPI1_NPCS1 I/O VDDIOP0 SCK1 I/O VDDIOP0 SCK2 I/O VDDIOP0 PWM1 I/O VDDIOP0 SAM9G46 Function Comments TSAD0 TSAD1 TSAD2 TSAD3 GPAD4 GPAD5 GPAD6 GPAD7 45 ...
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... LCDD12 PE20 LCDD13 PE21 LCDD14 PE22 LCDD15 PE23 LCDD16 PE24 LCDD17 PE25 LCDD18 PE26 LCDD19 PE27 LCDD20 PE28 LCDD21 PE29 LCDD22 PE30 LCDD23 PE31 PWM2 SAM9G46 46 Reset Power Peripheral B State Supply PCK0 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 I/O VDDIOP1 LCDD2 I/O VDDIOP1 ...
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... Parity generation and error detection – Framing error detection, overrun error detection – MSB- or LSB-first – Optional break generation and detection – by-16 over-sampling receiver frequency – Hardware handshaking RTS-CTS 11028CS–ATARM–20-Apr-11 peripherals Sensors and data per chip select SAM9G46 47 ...
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... Offers a configurable frame sync and data length • Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal • Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal SAM9G46 TDM Buses, Magnetic Card Reader,...) 11028CS–ATARM–20-Apr-11 ...
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... Independent channel programming – Independent Enable Disable Commands – Independent Clock Selection – Independent Period and Duty Cycle, with Double Buffering – Programmable selection of the output waveform polarity – Programmable center or left aligned output waveform 11028CS–ATARM–20-Apr-11 SAM9G46 49 ...
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... STN • bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT • Single clock domain architecture • Resolution supported up to 2048 x 2048 SAM9G46 50 11028CS–ATARM–20-Apr-11 ...
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... Support for ITU-R BT.656-4 SAV and EAV synchronization • Vertical and horizontal resolutions up to 2048 x 2048 • Preview Path up to 640*480 • Support for packed data formatting for YCbCr 4:2:2 formats 11028CS–ATARM–20-Apr-11 enabled channels ® Standard 802.3 SAM9G46 51 ...
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... Passed NIST Special Publication 800-22 Tests Suite • Passed Diehard Random Tests Suite • Provides a 32-bit Random Number Every 84 Clock Cycles • For 133 MHz Clock Frequency, Throughput Close to 50 Mbits/s SAM9G46 52 lists transfer. Writing a stream of data into non-contiguous fields in system memory ...
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... Last Output Data Mode Allows Optimized Message (Data) Authentication Code (MAC) Generation • Connection to PDC Channel Capabilities Optimizes Data Transfers for all Operating Modes – One Channel for the Receiver, One Channel for the Transmitter – Next Buffer Support 11028CS–ATARM–20-Apr-11 SAM9G46 53 ...
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... Clock Cycles to Maximize the Bandwidth for SHA256 or 265 Clock Cycles or • Connection to PDC Channel Capabilities Optimizes Data Transfers – One Channel for the Transmitter – Next Buffer Support SAM9G46 54 Applications in PDC (Peripheral DMA) Other Applications in PDC (Peripheral DMA) 11028CS–ATARM–20-Apr-11 ...
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... Mechanical Characteristics 11.1 Package Drawings Figure 11-1. 324-ball TFBGA Package Drawing 11028CS–ATARM–20-Apr-11 SAM9G46 55 ...
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... SAM9G46 Ordering Information Table 12-1. AT91SAM9G46 Ordering Information Ordering Code AT91SAM9G46-CU SAM9G46 56 Package Package Type TFBGA324 Green Temperature Operating Range Industrial -40°C to 85°C 11028CS–ATARM–20-Apr-11 ...
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... Revision History Doc. Rev Comments Introduction Product Line/Product naming convention changed - AT91SAM ARM-based MPU / SAM9G46 11028CS Section 5.1 “Power Supplies”, replaced ground pin names by GNDIOM, GNDCORE, GNDANA, GNDIOP, GNDBU, GNDOSC, GNDUTMI. Reorganized text describing GND association to power supply pins 11028BS ‘11-layer --> ‘12-layer’ in ...
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