SAM9G46 Atmel Corporation, SAM9G46 Datasheet - Page 32

• Manufacturer Part Number: SAM9G46
• Manufacturer: Atmel Corporation

Specifications of SAM9G46

• Flash (kbytes): 0 Kbytes
• Pin Count: 324
• Max. Operating Frequency: 400 MHz
• Cpu: ARM926
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 160
• Ext Interrupts: 160
• Usb Transceiver: 3
• Usb Speed: Hi-Speed
• Usb Interface: Host, Device
• Spi: 2
• Twi (i2c): 2
• Uart: 5
• Lin: 4
• Ssc: 2
• Ethernet: 1
• Sd / Emmc: 2
• Graphic Lcd: Yes
• Video Decoder: No
• Camera Interface: Yes
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 440
• Resistive Touch Screen: Yes
• Temp. Sensor: No
• Crypto Engine: AES/DES
• Sram (kbytes): 64
• Self Program Memory: NO
• External Bus Interface: 2
• Dram Memory: DDR2/LPDDR, SDRAM/LPSDR
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.8/3.3
• Operating Voltage (vcc): 0.9 to 1.1
• Fpu: No
• Mpu / Mmu: No/Yes
• Timers: 6
• Output Compare Channels: 6
• Input Capture Channels: 6
• Pwm Channels: 4
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: No

8.3
8.4
8.5
32
Reset Controller
Shut Down Controller
Clock Generator
SAM9G46
The Reset Controller is based on two Power-on-Reset cells, one on VDDBU and one on
VDDCORE.
The Reset Controller is capable to return to the software the source of the last reset, either a
general reset (VDDBU rising), a wake-up reset (VDDCORE rising), a software reset, a user
reset or a watchdog reset.
The Reset Controller controls the internal resets of the system and the NRST pin output. It is
capable to shape a reset signal for the external devices, simplifying to a minimum connection of
a push-button on the NRST pin to implement a manual reset.
The configuration of the Reset Controller is saved as supplied on VDDBU.
The Shut Down Controller is supplied on VDDBU and allows a software-controllable shut down
of the system through the pin SHDN. An input change of the WKUP pin or an alarm releases the
SHDN pin, and thus wakes up the system power supply.
The Clock Generator is made up of:
The USB Device and Host HS Clocks are provided by a the dedicated UTMI PLL (UPLL)
embedded in the UTMI macro.
• One Low Power 32768 Hz Slow Clock Oscillator with bypass mode
• One Low-Power RC oscillator
• One 12 MHz Main Oscillator, which can be bypassed
• One 400 to 800 MHz programmable PLLA, capable to provide the clock MCK to the
processor and to the peripherals. This PLL has an input divider to offer a wider range of
output frequencies from the 12 MHz input, the only limitation being the lowest input frequency
shall be higher or equal to 2 MHz.
11028CS–ATARM–20-Apr-11